From 0792ab0eb630da4a46b117367f86a6c7a8ab94a0 Mon Sep 17 00:00:00 2001
From: Alan Mishchenko <alanmi@berkeley.edu>
Date: Wed, 21 Mar 2012 23:19:49 -0700
Subject: Additional features for delay optimization

---
 src/base/abci/abcIf.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/base/abci/abcIf.c')

diff --git a/src/base/abci/abcIf.c b/src/base/abci/abcIf.c
index 2d6915e4..f2b101b9 100644
--- a/src/base/abci/abcIf.c
+++ b/src/base/abci/abcIf.c
@@ -209,7 +209,8 @@ If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
     Abc_NtkForEachCi( pNtk, pNode, i )
     {
         pNode->pCopy = (Abc_Obj_t *)If_ManCreateCi( pIfMan );
-//printf( "AIG CI %2d -> IF CI %2d\n", pNode->Id, ((If_Obj_t *)pNode->pCopy)->Id );
+        // transfer logic level information
+        ((If_Obj_t *)pNode->pCopy)->Level = pNode->Level;
     }
 
     // load the AIG into the mapper
-- 
cgit v1.2.3