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* Code restructuring.Alan Mishchenko2014-09-166-316/+422
* Improvements to Boolean matching.Alan Mishchenko2014-09-162-201/+568
* Compiler error (duplicate typedef).Alan Mishchenko2014-09-151-1/+0
* Compiler warnings.Alan Mishchenko2014-09-124-47/+47
* Replacing tabs with spaces.Alan Mishchenko2014-09-121-1/+1
* New word-level representation package.Alan Mishchenko2014-09-1213-61/+2243
* Resetting the random seed in 'sparsify'.Alan Mishchenko2014-09-111-0/+1
* Updating timing info during normalization.Alan Mishchenko2014-09-101-1/+1
* Updating timing info during normalization.Alan Mishchenko2014-09-101-1/+3
* Bug fix in transferring timing info.Alan Mishchenko2014-09-093-6/+63
* Corner-case bug fix in balancing.Alan Mishchenko2014-09-081-0/+2
* Added command 'move_names'.Alan Mishchenko2014-08-281-1/+1
* Added command 'move_names'.Alan Mishchenko2014-08-282-0/+106
* Tuning LUT mapping flow.Alan Mishchenko2014-08-282-1/+5
* Tuning LUT mapping flow.Alan Mishchenko2014-08-272-4/+6
* Compiler warning.Alan Mishchenko2014-08-271-2/+2
* Tuning LUT mapping flow.Alan Mishchenko2014-08-272-0/+254
* Improvements BLIF parser.Alan Mishchenko2014-08-273-4/+130
* Improvements to DSD balancing.Alan Mishchenko2014-08-276-43/+109
* Adding commands to save/load best network.Alan Mishchenko2014-08-266-9/+342
* Improvements to the timing manager.Alan Mishchenko2014-08-255-12/+15
* Improving GIA interfaces for some procedures.Alan Mishchenko2014-08-258-54/+70
* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-257-44/+172
* Improving print-out of 'dsd -p'.Alan Mishchenko2014-08-224-1/+154
* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-209-41/+34
* Extended command &cone to extract timing critical cones.Alan Mishchenko2014-08-193-39/+141
* Added command 'sparsify' to derive ISF from CSF.Alan Mishchenko2014-08-182-0/+212
* Changing default CNF generation in &bmc.Alan Mishchenko2014-08-183-1/+9
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-162-2/+2
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-2/+3
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-161-1/+1
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-0/+1
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-165-0/+132
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-164-5/+436
* Suggested fix to allow .constr files to have empty lines.Alan Mishchenko2014-08-131-0/+2
* Enabling circuit solver in &fraig.Alan Mishchenko2014-08-126-13/+100
* Bug fix in &fraig -L <num>.Alan Mishchenko2014-08-121-2/+2
* Bug fix in &fraig -L <num>.Alan Mishchenko2014-08-123-4/+15
* Increasing the size of pre-allocated memory in &syn2.Alan Mishchenko2014-08-111-1/+1
* Adding delay optimization to synthesis script &syn2.Alan Mishchenko2014-08-087-22/+119
* Enabling cofactoring in the mapper.Alan Mishchenko2014-08-062-2/+23
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-041-0/+69
* Compiler warnings.Alan Mishchenko2014-08-045-11/+67
* Enabling ISOP-based minimization in 'collapse' if EXDC is available.Alan Mishchenko2014-08-042-2/+35
* Compiler warnings.Alan Mishchenko2014-08-022-1/+2
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-025-0/+465
* Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, ...Alan Mishchenko2014-08-021-4/+26
* Small changes.Alan Mishchenko2014-07-292-3/+4
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-285-10/+147
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-261-1/+1
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