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yosys-experimental
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Author
Age
Files
Lines
...
*
User-controlable SAT sweeper.
Alan Mishchenko
2013-02-25
1
-0
/
+5
*
Integrating sweeping information.
Alan Mishchenko
2013-02-23
1
-1
/
+3
*
Integrating sweeping information.
Alan Mishchenko
2013-02-23
2
-3
/
+5
*
Allowing for Verilog names of the type slash-<name>-space-[N].
Alan Mishchenko
2013-02-22
1
-2
/
+8
*
Integrating sweeping information.
Alan Mishchenko
2013-02-20
1
-0
/
+1
*
Integrating sweeping information.
Alan Mishchenko
2013-02-20
1
-7
/
+8
*
Integrating sweeping information.
Alan Mishchenko
2013-02-20
1
-1
/
+1
*
Integrating hierarchy information (reporting incorrect topological order).
Alan Mishchenko
2013-02-20
2
-0
/
+24
*
Adding STG generation (&era -d) and STG encoding (&read_stg <file>).
Alan Mishchenko
2013-02-19
1
-0
/
+1
*
Integrating sweeping information.
Alan Mishchenko
2013-02-19
1
-27
/
+35
*
Integrating sweeping information.
Alan Mishchenko
2013-02-18
2
-6
/
+136
*
Integration of timing manager.
Alan Mishchenko
2013-02-03
1
-1
/
+1
*
Integration of timing manager.
Alan Mishchenko
2013-02-01
1
-0
/
+1
*
Integration of timing manager.
Alan Mishchenko
2013-01-30
1
-0
/
+2
*
Fixing compilation problems on Linux-32 related to constants of type unsigned...
Alan Mishchenko
2013-01-30
3
-80
/
+86
*
Updated CEX code to handle trivial CEX of the type (Abc_Cex_t*)1.
Alan Mishchenko
2013-01-25
1
-0
/
+19
*
Integration of timing manager.
Alan Mishchenko
2013-01-25
1
-3
/
+10
*
Enabled detecting CEXes in multiple POs without stopping (sim3 -a).
Alan Mishchenko
2013-01-23
1
-1
/
+2
*
Integration of timing manager.
Alan Mishchenko
2013-01-23
1
-2
/
+4
*
Fixing C++ compilation issues.
Alan Mishchenko
2013-01-08
2
-4
/
+8
*
Technology mapper.
Alan Mishchenko
2013-01-08
1
-0
/
+253
*
Assembling timing/hierarchy manager from input data.
Alan Mishchenko
2012-12-15
2
-5
/
+51
*
Assembling timing/hierarchy manager from input data.
Alan Mishchenko
2012-12-13
2
-10
/
+22
*
Assembling timing/hierarchy manager from input data.
Alan Mishchenko
2012-12-10
2
-0
/
+62
*
Unifification of custom extensions.
Alan Mishchenko
2012-12-10
3
-32
/
+31
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-3
/
+4
*
Deriving CEX after phase/tempor/reparam.
Alan Mishchenko
2012-12-09
1
-6
/
+5
*
Deriving CEX after phase/tempor/reparam.
Alan Mishchenko
2012-12-08
2
-1
/
+118
*
Counter-example analysis and optimization.
Alan Mishchenko
2012-11-30
1
-2
/
+2
*
Counter-example analysis and optimization.
Alan Mishchenko
2012-11-29
2
-0
/
+20
*
Counter-example analysis and optimization.
Alan Mishchenko
2012-11-28
2
-0
/
+12
*
DSD manager.
Alan Mishchenko
2012-11-20
1
-5
/
+5
*
DSD manager.
Alan Mishchenko
2012-11-19
1
-0
/
+1
*
Added switch 'cexcut -m' to generate bad states for all frames after G.
Alan Mishchenko
2012-11-15
1
-2
/
+2
*
Added command 'cexcut' and 'cexmerge'.
Alan Mishchenko
2012-11-14
1
-11
/
+12
*
Added command 'cexcut' and 'cexmerge'.
Alan Mishchenko
2012-11-14
2
-0
/
+59
*
Made print-out of frontier cut an option ('-c') in '&ps'.
Alan Mishchenko
2012-11-12
1
-1
/
+1
*
Improved DSD.
Alan Mishchenko
2012-11-11
1
-3
/
+46
*
Improved DSD.
Alan Mishchenko
2012-11-06
1
-0
/
+52
*
Improved DSD.
Alan Mishchenko
2012-11-06
1
-45
/
+164
*
Improved DSD.
Alan Mishchenko
2012-11-03
1
-1
/
+2
*
Improved DSD.
Alan Mishchenko
2012-11-02
1
-21
/
+36
*
Improvements to the truth table computations.
Alan Mishchenko
2012-11-01
1
-10
/
+2
*
Improvements to the truth table computations.
Alan Mishchenko
2012-11-01
1
-462
/
+69
*
Improvements to the truth table computations.
Alan Mishchenko
2012-11-01
1
-84
/
+101
*
Improvements to the truth table computations.
Alan Mishchenko
2012-10-31
1
-13
/
+22
*
Improvements to the truth table computations.
Alan Mishchenko
2012-10-31
1
-2
/
+4
*
Improvements to the truth table computations.
Alan Mishchenko
2012-10-31
1
-2
/
+38
*
Improvements to the truth table computations.
Alan Mishchenko
2012-10-30
1
-2
/
+39
*
Improvements to the truth table computations.
Alan Mishchenko
2012-10-30
1
-4
/
+4
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