Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Adding switch to &if to consider special type of 6-input cuts. | Alan Mishchenko | 2019-09-26 | 4 | -0/+84 |
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* | Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to ↵ | Alan Mishchenko | 2019-09-19 | 1 | -0/+1 |
| | | | | print delay profile. | ||||
* | Fixing some update gcc. | Alan Mishchenko | 2019-07-24 | 1 | -1/+1 |
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* | Adding support for user-specified wire delays in &if. | Alan Mishchenko | 2019-05-29 | 1 | -1/+1 |
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* | Prevent assertions from firing for deep logic networks. | Alan Mishchenko | 2019-03-20 | 1 | -4/+4 |
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* | Fixing some warnings by adding cast from 'int' to 'size_t' in memset, ↵ | Alan Mishchenko | 2019-03-05 | 17 | -26/+26 |
| | | | | memcpy, etc. | ||||
* | Fixing some warnings with -Wconversion. | Alan Mishchenko | 2019-03-05 | 1 | -2/+2 |
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* | Fixing float overflow during edge-flow computation in 'if' mapper (change to ↵ | Alan Mishchenko | 2018-12-12 | 1 | -0/+8 |
| | | | | avoid dependence on the order of additions). | ||||
* | Fixing float overflow during edge-flow computation in 'if' mapper. | Alan Mishchenko | 2018-12-12 | 1 | -3/+7 |
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* | Adding switch &w -n to modify the comment section of the AIGER file written. | Alan Mishchenko | 2018-11-21 | 1 | -2/+2 |
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* | Skip cells in Liberty files which have dont_use attribute. | Alan Mishchenko | 2018-10-18 | 2 | -3/+56 |
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* | Suggested bug fix in 'amap'. | Alan Mishchenko | 2018-09-13 | 1 | -0/+3 |
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* | Adding parameters and improvements to %blast. | Alan Mishchenko | 2018-02-28 | 2 | -0/+8 |
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* | Compilation problem with pow(). | Alan Mishchenko | 2018-02-19 | 1 | -2/+2 |
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* | Value of properties can be expression. | Staf Verhaegen | 2018-01-03 | 1 | -0/+12 |
| | | | | | | | | | | | | | | Example found in the 2007.03 Liberty Reference Manual that was also found in the wild: input_voltage(CMOS) { vil : 0.3 * VDD ; vih : 0.7 * VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; } Current implementation just parses the expression but no interpretation is done. | ||||
* | Adding API to dump MiniAIG into a Verilog file and other small changes. | Alan Mishchenko | 2017-10-22 | 2 | -0/+3 |
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* | Fix typo on the message reporting max output load. | Alan Mishchenko | 2017-10-11 | 1 | -1/+1 |
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* | Updates and bug fixes. | Alan Mishchenko | 2017-10-04 | 3 | -11/+19 |
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* | Maintenance and updates. | Alan Mishchenko | 2017-09-24 | 5 | -3/+57 |
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* | Maintenance and updates. | Alan Mishchenko | 2017-09-20 | 2 | -3/+7 |
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* | Maintenance and updates. | Alan Mishchenko | 2017-09-18 | 4 | -0/+56 |
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* | Compiler warnings. | Alan Mishchenko | 2017-07-22 | 6 | -8/+8 |
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* | Synchronizing various data-structures. | Alan Mishchenko | 2017-07-04 | 2 | -7/+162 |
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* | Saturating floating point computation. | Alan Mishchenko | 2017-07-01 | 1 | -3/+7 |
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* | Saturating floating point computation. | Alan Mishchenko | 2017-06-29 | 1 | -4/+10 |
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* | Experiments with new network data-structure. | Alan Mishchenko | 2017-03-20 | 2 | -0/+2 |
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* | Experiments with new network data-structure. | Alan Mishchenko | 2017-03-19 | 1 | -1/+1 |
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* | stringizing macro argument | Heinz Riener | 2017-03-03 | 1 | -2/+2 |
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* | Restoring constraint manager to read old constraint file by default (use ↵ | Alan Mishchenko | 2017-02-25 | 2 | -18/+26 |
| | | | | 'read_constr -n' to read new format). | ||||
* | Corner-case bug-fix in library preprocessor for standard-cell mapping. | Alan Mishchenko | 2017-02-05 | 1 | -2/+2 |
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* | Typo. | Alan Mishchenko | 2017-01-31 | 1 | -1/+1 |
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* | Bug fixes by Clifford Wolf. | Alan Mishchenko | 2017-01-08 | 1 | -0/+4 |
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* | Compiler warnings. | Alan Mishchenko | 2017-01-07 | 2 | -5/+5 |
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* | Compiler warnings. | Alan Mishchenko | 2016-12-31 | 1 | -3/+3 |
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* | Bug fix in Liberty parser. | Alan Mishchenko | 2016-12-05 | 1 | -0/+4 |
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* | Equivalent fault detection code. | Alan Mishchenko | 2016-11-09 | 3 | -0/+5 |
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* | Memory leak in scl package. | Alan Mishchenko | 2016-10-12 | 1 | -0/+2 |
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* | Adding truth table occurrence counters for 'if -c'. | Alan Mishchenko | 2016-08-08 | 3 | -0/+14 |
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* | Enabled progress bar in the 'if' mapper (warning). | Alan Mishchenko | 2016-08-08 | 1 | -1/+1 |
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* | Enabled delay computation for the cut output using cut inputs. | Alan Mishchenko | 2016-08-08 | 3 | -2/+52 |
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* | Enabled progress bar in the 'if' mapper. | Alan Mishchenko | 2016-08-08 | 1 | -5/+5 |
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* | Adding one argument to the delay-estimation API used for exact synthesis. | Alan Mishchenko | 2016-07-31 | 1 | -3/+3 |
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* | Infrastructure for using the results of exact SAT-based synthesis during ↵ | Alan Mishchenko | 2016-07-29 | 1 | -3/+25 |
| | | | | mapping. | ||||
* | Infrastructure for using the results of exact SAT-based synthesis during ↵ | Alan Mishchenko | 2016-07-29 | 3 | -17/+33 |
| | | | | mapping. | ||||
* | Adding switch -P <num> to command 'cover'. | Alan Mishchenko | 2016-06-14 | 3 | -6/+6 |
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* | New feature for area minimization in standard cell mapping. | Alan Mishchenko | 2016-05-19 | 1 | -0/+5 |
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* | Factoring out library preprocessing code in &nf and putting it elsewhere. | Alan Mishchenko | 2016-05-16 | 3 | -0/+59 |
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* | Added switch 'read_genlib -n' to anonymize Genlib library. | Alan Mishchenko | 2016-05-16 | 3 | -9/+139 |
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* | Adding option to rehash AIG after mapping. | Alan Mishchenko | 2016-04-27 | 1 | -0/+1 |
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* | Adding API to convert Genlib into a simple Liberty. | Alan Mishchenko | 2016-03-11 | 4 | -1/+145 |
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