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yosys-experimental
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Age
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*
Adding commands to read/write/print gate profiles.
Alan Mishchenko
2015-12-05
5
-8
/
+250
*
Improvements to timing optimization.
Alan Mishchenko
2015-11-11
4
-10
/
+12
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
6
-13
/
+78
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
2
-4
/
+9
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
4
-3
/
+161
*
silence clang errors when compiling as C++
Baruch Sterin
2015-11-05
1
-1
/
+1
*
Bug fix in constructing internal choices by 'amap'.
Alan Mishchenko
2015-11-04
1
-1
/
+1
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-27
2
-0
/
+2
*
Changes for delay-oriented computation.
Alan Mishchenko
2015-10-26
1
-1
/
+1
*
Extending library handling to 8 inputs.
Alan Mishchenko
2015-10-25
3
-2
/
+62
*
Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.
Alan Mishchenko
2015-10-23
3
-16
/
+38
*
Changes for delay-oriented computation.
Alan Mishchenko
2015-10-23
2
-2
/
+4
*
Compiler warnings.
Alan Mishchenko
2015-10-21
1
-2
/
+2
*
Moving BDD-based threshold function detection to the BDD part of the code.
Alan Mishchenko
2015-10-16
2
-0
/
+9
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-15
2
-0
/
+2
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-12
4
-15
/
+31
*
Two fixes in 'dsd_filter'.
Alan Mishchenko
2015-10-07
1
-1
/
+1
*
Bug fix in 'if -g' (incorrect use of a macro).
Alan Mishchenko
2015-10-07
1
-3
/
+3
*
Improvements to Scl_Lib/SC_Cell data-structure.
Alan Mishchenko
2015-09-24
6
-230
/
+211
*
Several bug-fixed related to synthesis, library handling, and timimg info.
Alan Mishchenko
2015-09-23
1
-2
/
+4
*
Threshold logic checking code by Augusto Neutzling and Jody Matos.
Alan Mishchenko
2015-09-23
1
-3
/
+6
*
New constraint manager and memory reporting 'ps'.
Alan Mishchenko
2015-09-08
5
-16
/
+425
*
Updating Mio to use int instead of float.
Alan Mishchenko
2015-08-31
2
-2
/
+192
*
Alternative way to bit-blast a divisor.
Alan Mishchenko
2015-08-29
1
-1
/
+1
*
Important bug fixes in standard-cell library handling and mapper &nf.
Alan Mishchenko
2015-08-28
4
-14
/
+34
*
Changes to be able to compile ABC without CUDD.
Alan Mishchenko
2015-08-24
2
-1
/
+3
*
New switch in 'read_lib' to replace gate/pin names by short strings.
Alan Mishchenko
2015-08-24
1
-5
/
+44
*
New switch in 'read_lib' to replace gate/pin names by short strings.
Alan Mishchenko
2015-08-24
3
-2
/
+105
*
Experiments with mapping plus small changes.
Alan Mishchenko
2015-08-23
3
-3
/
+10
*
Small changes to enable collecting results using &ps -D file.
Alan Mishchenko
2015-07-09
2
-0
/
+2
*
Bug fix in programmable cell parser and minor tuning.
Alan Mishchenko
2015-07-08
1
-1
/
+2
*
C++ compiler typecast problem.
Alan Mishchenko
2015-07-08
1
-1
/
+1
*
Add fix to Liberty parser to skip extra semicolon.
Alan Mishchenko
2015-07-06
1
-0
/
+5
*
Undo recent assert.
Alan Mishchenko
2015-06-27
1
-2
/
+2
*
Potential performance bug in the mapper.
Alan Mishchenko
2015-06-27
1
-1
/
+1
*
Supporting AND-gate cuts in 'if' and '&if'
Alan Mishchenko
2015-06-21
3
-6
/
+27
*
Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.
Alan Mishchenko
2015-05-15
1
-2
/
+7
*
Making sure 0-input LUTs are supported by the DSD matching code.
Alan Mishchenko
2015-05-14
1
-5
/
+5
*
Improving the criteria to select representative gates in 'map' with floating-...
Alan Mishchenko
2015-04-25
1
-47
/
+60
*
Adding switch 'map -f' to not use large gates for high-fanout nodes (disabled...
Alan Mishchenko
2015-04-24
4
-2
/
+5
*
Adding platform-independent (alphabetic) way of sorting Genlib gates and sele...
Alan Mishchenko
2015-04-17
2
-20
/
+56
*
Adding APIs to retrieve NOR/OR gates from the library.
Alan Mishchenko
2015-04-14
4
-4
/
+15
*
Getting default AND-node delay from Genlib library.
Alan Mishchenko
2015-04-06
2
-0
/
+2
*
Support for representing programmable cell configuration data (bug fix).
Alan Mishchenko
2015-03-09
1
-1
/
+4
*
Support for representing programmable cell configuration data.
Alan Mishchenko
2015-03-08
1
-1
/
+2
*
Support for representing programmable cell configuration data.
Alan Mishchenko
2015-03-08
3
-64
/
+222
*
Experiments with SAT-based cube enumeration.
Alan Mishchenko
2015-03-05
1
-3
/
+4
*
Corner case bug in wire-cap estimation.
Alan Mishchenko
2015-02-18
1
-0
/
+2
*
Several improvements to CBA data-structure.
Alan Mishchenko
2015-02-09
1
-1
/
+1
*
Fixed a typo in variable names.
Alan Mishchenko
2015-02-07
5
-24
/
+24
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