summaryrefslogtreecommitdiffstats
path: root/src/map
Commit message (Expand)AuthorAgeFilesLines
* Prevent assertions from firing for deep logic networks.Alan Mishchenko2019-03-201-4/+4
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-0517-26/+26
* Fixing some warnings with -Wconversion.Alan Mishchenko2019-03-051-2/+2
* Fixing float overflow during edge-flow computation in 'if' mapper (change to ...Alan Mishchenko2018-12-121-0/+8
* Fixing float overflow during edge-flow computation in 'if' mapper.Alan Mishchenko2018-12-121-3/+7
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-2/+2
* Skip cells in Liberty files which have dont_use attribute.Alan Mishchenko2018-10-182-3/+56
* Suggested bug fix in 'amap'.Alan Mishchenko2018-09-131-0/+3
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-282-0/+8
* Compilation problem with pow().Alan Mishchenko2018-02-191-2/+2
* Value of properties can be expression.Staf Verhaegen2018-01-031-0/+12
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-222-0/+3
* Fix typo on the message reporting max output load.Alan Mishchenko2017-10-111-1/+1
* Updates and bug fixes.Alan Mishchenko2017-10-043-11/+19
* Maintenance and updates.Alan Mishchenko2017-09-245-3/+57
* Maintenance and updates.Alan Mishchenko2017-09-202-3/+7
* Maintenance and updates.Alan Mishchenko2017-09-184-0/+56
* Compiler warnings.Alan Mishchenko2017-07-226-8/+8
* Synchronizing various data-structures.Alan Mishchenko2017-07-042-7/+162
* Saturating floating point computation.Alan Mishchenko2017-07-011-3/+7
* Saturating floating point computation.Alan Mishchenko2017-06-291-4/+10
* Experiments with new network data-structure.Alan Mishchenko2017-03-202-0/+2
* Experiments with new network data-structure.Alan Mishchenko2017-03-191-1/+1
* stringizing macro argumentHeinz Riener2017-03-031-2/+2
* Restoring constraint manager to read old constraint file by default (use 'rea...Alan Mishchenko2017-02-252-18/+26
* Corner-case bug-fix in library preprocessor for standard-cell mapping.Alan Mishchenko2017-02-051-2/+2
* Typo.Alan Mishchenko2017-01-311-1/+1
* Bug fixes by Clifford Wolf.Alan Mishchenko2017-01-081-0/+4
* Compiler warnings.Alan Mishchenko2017-01-072-5/+5
* Compiler warnings.Alan Mishchenko2016-12-311-3/+3
* Bug fix in Liberty parser.Alan Mishchenko2016-12-051-0/+4
* Equivalent fault detection code.Alan Mishchenko2016-11-093-0/+5
* Memory leak in scl package.Alan Mishchenko2016-10-121-0/+2
* Adding truth table occurrence counters for 'if -c'.Alan Mishchenko2016-08-083-0/+14
* Enabled progress bar in the 'if' mapper (warning).Alan Mishchenko2016-08-081-1/+1
* Enabled delay computation for the cut output using cut inputs.Alan Mishchenko2016-08-083-2/+52
* Enabled progress bar in the 'if' mapper.Alan Mishchenko2016-08-081-5/+5
* Adding one argument to the delay-estimation API used for exact synthesis.Alan Mishchenko2016-07-311-3/+3
* Infrastructure for using the results of exact SAT-based synthesis during mapp...Alan Mishchenko2016-07-291-3/+25
* Infrastructure for using the results of exact SAT-based synthesis during mapp...Alan Mishchenko2016-07-293-17/+33
* Adding switch -P <num> to command 'cover'.Alan Mishchenko2016-06-143-6/+6
* New feature for area minimization in standard cell mapping.Alan Mishchenko2016-05-191-0/+5
* Factoring out library preprocessing code in &nf and putting it elsewhere.Alan Mishchenko2016-05-163-0/+59
* Added switch 'read_genlib -n' to anonymize Genlib library.Alan Mishchenko2016-05-163-9/+139
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-271-0/+1
* Adding API to convert Genlib into a simple Liberty.Alan Mishchenko2016-03-114-1/+145
* Disabling formula cleaner to avoid problems with reading GENLIB on some libra...Alan Mishchenko2016-02-211-1/+2
* Bug fix in liberty parser and change suggested by Clifford.Alan Mishchenko2016-02-072-1/+17
* GENLIB parsing bug, which led to a crash.Alan Mishchenko2016-02-061-1/+4
* Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...Alan Mishchenko2016-01-301-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 12:26:31 +0000