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yosys-experimental
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Age
Files
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*
Experiments with new network data-structure.
Alan Mishchenko
2017-03-20
2
-0
/
+2
*
Experiments with new network data-structure.
Alan Mishchenko
2017-03-19
1
-1
/
+1
*
stringizing macro argument
Heinz Riener
2017-03-03
1
-2
/
+2
*
Restoring constraint manager to read old constraint file by default (use 'rea...
Alan Mishchenko
2017-02-25
2
-18
/
+26
*
Corner-case bug-fix in library preprocessor for standard-cell mapping.
Alan Mishchenko
2017-02-05
1
-2
/
+2
*
Typo.
Alan Mishchenko
2017-01-31
1
-1
/
+1
*
Bug fixes by Clifford Wolf.
Alan Mishchenko
2017-01-08
1
-0
/
+4
*
Compiler warnings.
Alan Mishchenko
2017-01-07
2
-5
/
+5
*
Compiler warnings.
Alan Mishchenko
2016-12-31
1
-3
/
+3
*
Bug fix in Liberty parser.
Alan Mishchenko
2016-12-05
1
-0
/
+4
*
Equivalent fault detection code.
Alan Mishchenko
2016-11-09
3
-0
/
+5
*
Memory leak in scl package.
Alan Mishchenko
2016-10-12
1
-0
/
+2
*
Adding truth table occurrence counters for 'if -c'.
Alan Mishchenko
2016-08-08
3
-0
/
+14
*
Enabled progress bar in the 'if' mapper (warning).
Alan Mishchenko
2016-08-08
1
-1
/
+1
*
Enabled delay computation for the cut output using cut inputs.
Alan Mishchenko
2016-08-08
3
-2
/
+52
*
Enabled progress bar in the 'if' mapper.
Alan Mishchenko
2016-08-08
1
-5
/
+5
*
Adding one argument to the delay-estimation API used for exact synthesis.
Alan Mishchenko
2016-07-31
1
-3
/
+3
*
Infrastructure for using the results of exact SAT-based synthesis during mapp...
Alan Mishchenko
2016-07-29
1
-3
/
+25
*
Infrastructure for using the results of exact SAT-based synthesis during mapp...
Alan Mishchenko
2016-07-29
3
-17
/
+33
*
Adding switch -P <num> to command 'cover'.
Alan Mishchenko
2016-06-14
3
-6
/
+6
*
New feature for area minimization in standard cell mapping.
Alan Mishchenko
2016-05-19
1
-0
/
+5
*
Factoring out library preprocessing code in &nf and putting it elsewhere.
Alan Mishchenko
2016-05-16
3
-0
/
+59
*
Added switch 'read_genlib -n' to anonymize Genlib library.
Alan Mishchenko
2016-05-16
3
-9
/
+139
*
Adding option to rehash AIG after mapping.
Alan Mishchenko
2016-04-27
1
-0
/
+1
*
Adding API to convert Genlib into a simple Liberty.
Alan Mishchenko
2016-03-11
4
-1
/
+145
*
Disabling formula cleaner to avoid problems with reading GENLIB on some libra...
Alan Mishchenko
2016-02-21
1
-1
/
+2
*
Bug fix in liberty parser and change suggested by Clifford.
Alan Mishchenko
2016-02-07
2
-1
/
+17
*
GENLIB parsing bug, which led to a crash.
Alan Mishchenko
2016-02-06
1
-1
/
+4
*
Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...
Alan Mishchenko
2016-01-30
1
-1
/
+1
*
Adding support for delay/area tradeoff.
Alan Mishchenko
2016-01-13
1
-3
/
+3
*
Consolidating timing manager Scl_Con_t and propagating changes.
Alan Mishchenko
2016-01-07
4
-16
/
+16
*
Bug fix in constraint file reader.
Alan Mishchenko
2016-01-07
2
-2
/
+8
*
Migrating to using 32-bit timing representation in &nf.
Alan Mishchenko
2016-01-05
3
-87
/
+87
*
Migrating back to using 'float' in area-flow computation in &nf.
Alan Mishchenko
2016-01-05
2
-7
/
+9
*
Corner-case bug in 'read_profile'.
Alan Mishchenko
2015-12-22
1
-1
/
+1
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-14
9
-51
/
+206
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-07
4
-1
/
+50
*
Adding commands to read/write/print gate profiles.
Alan Mishchenko
2015-12-05
5
-8
/
+250
*
Improvements to timing optimization.
Alan Mishchenko
2015-11-11
4
-10
/
+12
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
6
-13
/
+78
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
2
-4
/
+9
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
4
-3
/
+161
*
silence clang errors when compiling as C++
Baruch Sterin
2015-11-05
1
-1
/
+1
*
Bug fix in constructing internal choices by 'amap'.
Alan Mishchenko
2015-11-04
1
-1
/
+1
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-27
2
-0
/
+2
*
Changes for delay-oriented computation.
Alan Mishchenko
2015-10-26
1
-1
/
+1
*
Extending library handling to 8 inputs.
Alan Mishchenko
2015-10-25
3
-2
/
+62
*
Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.
Alan Mishchenko
2015-10-23
3
-16
/
+38
*
Changes for delay-oriented computation.
Alan Mishchenko
2015-10-23
2
-2
/
+4
*
Compiler warnings.
Alan Mishchenko
2015-10-21
1
-2
/
+2
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