iCE40/abc - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Experiments with mapping plus small changes.	Alan Mishchenko	2015-08-23	3	-3/+10
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*	Small changes to enable collecting results using &ps -D file.	Alan Mishchenko	2015-07-09	2	-0/+2
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*	Bug fix in programmable cell parser and minor tuning.	Alan Mishchenko	2015-07-08	1	-1/+2
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*	C++ compiler typecast problem.	Alan Mishchenko	2015-07-08	1	-1/+1
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*	Add fix to Liberty parser to skip extra semicolon.	Alan Mishchenko	2015-07-06	1	-0/+5
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*	Undo recent assert.	Alan Mishchenko	2015-06-27	1	-2/+2
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*	Potential performance bug in the mapper.	Alan Mishchenko	2015-06-27	1	-1/+1
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*	Supporting AND-gate cuts in 'if' and '&if'	Alan Mishchenko	2015-06-21	3	-6/+27
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*	Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.	Alan Mishchenko	2015-05-15	1	-2/+7
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*	Making sure 0-input LUTs are supported by the DSD matching code.	Alan Mishchenko	2015-05-14	1	-5/+5
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*	Improving the criteria to select representative gates in 'map' with ↵	Alan Mishchenko	2015-04-25	1	-47/+60
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*	Adding switch 'map -f' to not use large gates for high-fanout nodes ↵	Alan Mishchenko	2015-04-24	4	-2/+5
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*	Adding platform-independent (alphabetic) way of sorting Genlib gates and ↵	Alan Mishchenko	2015-04-17	2	-20/+56
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*	Adding APIs to retrieve NOR/OR gates from the library.	Alan Mishchenko	2015-04-14	4	-4/+15
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*	Getting default AND-node delay from Genlib library.	Alan Mishchenko	2015-04-06	2	-0/+2
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*	Support for representing programmable cell configuration data (bug fix).	Alan Mishchenko	2015-03-09	1	-1/+4
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*	Support for representing programmable cell configuration data.	Alan Mishchenko	2015-03-08	1	-1/+2
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*	Support for representing programmable cell configuration data.	Alan Mishchenko	2015-03-08	3	-64/+222
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*	Experiments with SAT-based cube enumeration.	Alan Mishchenko	2015-03-05	1	-3/+4
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*	Corner case bug in wire-cap estimation.	Alan Mishchenko	2015-02-18	1	-0/+2
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*	Several improvements to CBA data-structure.	Alan Mishchenko	2015-02-09	1	-1/+1
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*	Fixed a typo in variable names.	Alan Mishchenko	2015-02-07	5	-24/+24
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*	Improvements and tuning of CBA with buffering/sizing.	Alan Mishchenko	2015-02-04	5	-28/+77
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*	Improvements and tuning of CBA.	Alan Mishchenko	2015-02-01	1	-0/+2
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*	Major rehash of the CBA code.	Alan Mishchenko	2015-01-31	2	-0/+21
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*	New assertions and bug fix in DSD balancing.	Alan Mishchenko	2015-01-27	2	-8/+11
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*	Gate sizing with barrier buffers.	Alan Mishchenko	2014-12-21	3	-1/+52
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*	Exprimental features in tech-mapping.	Alan Mishchenko	2014-12-21	1	-2/+3
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*	Bug fix in reading box library.	Alan Mishchenko	2014-12-20	1	-1/+1
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*	Integrating barrier buffers.	Alan Mishchenko	2014-12-13	5	-10/+76
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*	Adding new mapping feature.	Alan Mishchenko	2014-12-11	4	-18/+56
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*	Integrating barrier buffers.	Alan Mishchenko	2014-12-08	1	-0/+8
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*	Bug fix in truth table computation.	Alan Mishchenko	2014-10-15	1	-11/+9
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*	Recommended changes for portability.	Alan Mishchenko	2014-10-12	1	-1/+1
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*	MUX decomposition during mapping.	Alan Mishchenko	2014-10-11	1	-1/+0
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*	Deriving network in terms of programmable cells.	Alan Mishchenko	2014-10-11	1	-1/+2
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*	Suggested patch for type-punned warnings	Alan Mishchenko	2014-10-10	1	-3/+6
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*	Small changes.	Alan Mishchenko	2014-10-08	1	-0/+2
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*	Compiler warnings.	Alan Mishchenko	2014-10-08	2	-1/+3
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*	Detection of threshold functions.	Alan Mishchenko	2014-10-08	2	-0/+74
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*	Deriving cell mapping with &if -kz.	Alan Mishchenko	2014-10-04	1	-2/+9
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*	Deriving cell mapping with &if -kz.	Alan Mishchenko	2014-10-04	3	-15/+126
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*	Deriving AIG after cell mapping.	Alan Mishchenko	2014-10-03	2	-0/+11
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*	Synchronizing packages.	Alan Mishchenko	2014-09-20	1	-0/+2
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*	Synchronizing packages.	Alan Mishchenko	2014-09-20	2	-3/+3
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*	Synchronizing packages.	Alan Mishchenko	2014-09-20	1	-0/+2
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*	Updating command 'dsd_clean'.	Alan Mishchenko	2014-09-20	3	-3/+16
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*	Updating DSD balance to handle XOR gate as having the same delay as AND gate.	Alan Mishchenko	2014-09-19	4	-10/+11
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*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-19	2	-33/+98
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*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-19	6	-66/+474
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