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* Support for representing programmable cell configuration data (bug fix).Alan Mishchenko2015-03-091-1/+4
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-1/+2
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-083-64/+222
* Experiments with SAT-based cube enumeration.Alan Mishchenko2015-03-051-3/+4
* Corner case bug in wire-cap estimation.Alan Mishchenko2015-02-181-0/+2
* Several improvements to CBA data-structure.Alan Mishchenko2015-02-091-1/+1
* Fixed a typo in variable names.Alan Mishchenko2015-02-075-24/+24
* Improvements and tuning of CBA with buffering/sizing.Alan Mishchenko2015-02-045-28/+77
* Improvements and tuning of CBA.Alan Mishchenko2015-02-011-0/+2
* Major rehash of the CBA code.Alan Mishchenko2015-01-312-0/+21
* New assertions and bug fix in DSD balancing.Alan Mishchenko2015-01-272-8/+11
* Gate sizing with barrier buffers.Alan Mishchenko2014-12-213-1/+52
* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-2/+3
* Bug fix in reading box library.Alan Mishchenko2014-12-201-1/+1
* Integrating barrier buffers.Alan Mishchenko2014-12-135-10/+76
* Adding new mapping feature.Alan Mishchenko2014-12-114-18/+56
* Integrating barrier buffers.Alan Mishchenko2014-12-081-0/+8
* Bug fix in truth table computation.Alan Mishchenko2014-10-151-11/+9
* Recommended changes for portability.Alan Mishchenko2014-10-121-1/+1
* MUX decomposition during mapping.Alan Mishchenko2014-10-111-1/+0
* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-1/+2
* Suggested patch for type-punned warningsAlan Mishchenko2014-10-101-3/+6
* Small changes.Alan Mishchenko2014-10-081-0/+2
* Compiler warnings.Alan Mishchenko2014-10-082-1/+3
* Detection of threshold functions.Alan Mishchenko2014-10-082-0/+74
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-2/+9
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-043-15/+126
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-032-0/+11
* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
* Synchronizing packages.Alan Mishchenko2014-09-202-3/+3
* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
* Updating command 'dsd_clean'.Alan Mishchenko2014-09-203-3/+16
* Updating DSD balance to handle XOR gate as having the same delay as AND gate.Alan Mishchenko2014-09-194-10/+11
* Improvements to Boolean matching.Alan Mishchenko2014-09-192-33/+98
* Improvements to Boolean matching.Alan Mishchenko2014-09-196-66/+474
* Improvements to Boolean matching.Alan Mishchenko2014-09-182-6/+22
* Improvements to Boolean matching.Alan Mishchenko2014-09-184-5/+29
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-14/+29
* Improving DSD manager.Alan Mishchenko2014-09-182-0/+69
* Concurrency for Boolean matching.Alan Mishchenko2014-09-184-47/+263
* Improvements to Boolean matching.Alan Mishchenko2014-09-173-60/+191
* Support for leakage power in Liberty parser and sizer.Alan Mishchenko2014-09-165-5/+122
* New choice computation.Alan Mishchenko2014-09-161-9/+9
* Improvements to Boolean matching.Alan Mishchenko2014-09-161-201/+554
* Improvements to the timing manager.Alan Mishchenko2014-08-251-2/+2
* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-251-1/+1
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-161-1/+1
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-164-0/+130
* Suggested fix to allow .constr files to have empty lines.Alan Mishchenko2014-08-131-0/+2
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-041-0/+69
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