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yosys-experimental
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Author
Age
Files
Lines
*
Equivalent fault detection code.
Alan Mishchenko
2016-11-09
3
-0
/
+5
*
New feature for area minimization in standard cell mapping.
Alan Mishchenko
2016-05-19
1
-0
/
+5
*
Factoring out library preprocessing code in &nf and putting it elsewhere.
Alan Mishchenko
2016-05-16
3
-0
/
+59
*
Added switch 'read_genlib -n' to anonymize Genlib library.
Alan Mishchenko
2016-05-16
3
-9
/
+139
*
Adding API to convert Genlib into a simple Liberty.
Alan Mishchenko
2016-03-11
2
-1
/
+2
*
Disabling formula cleaner to avoid problems with reading GENLIB on some libra...
Alan Mishchenko
2016-02-21
1
-1
/
+2
*
Bug fix in liberty parser and change suggested by Clifford.
Alan Mishchenko
2016-02-07
1
-1
/
+15
*
GENLIB parsing bug, which led to a crash.
Alan Mishchenko
2016-02-06
1
-1
/
+4
*
Consolidating timing manager Scl_Con_t and propagating changes.
Alan Mishchenko
2016-01-07
2
-6
/
+5
*
Migrating to using 32-bit timing representation in &nf.
Alan Mishchenko
2016-01-05
2
-16
/
+16
*
Migrating back to using 'float' in area-flow computation in &nf.
Alan Mishchenko
2016-01-05
2
-7
/
+9
*
Corner-case bug in 'read_profile'.
Alan Mishchenko
2015-12-22
1
-1
/
+1
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-14
3
-30
/
+71
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-07
4
-1
/
+50
*
Adding commands to read/write/print gate profiles.
Alan Mishchenko
2015-12-05
5
-8
/
+250
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
4
-1
/
+43
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
1
-0
/
+2
*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
2
-0
/
+3
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-27
2
-0
/
+2
*
Extending library handling to 8 inputs.
Alan Mishchenko
2015-10-25
2
-1
/
+61
*
Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.
Alan Mishchenko
2015-10-23
3
-16
/
+38
*
Changes for delay-oriented computation.
Alan Mishchenko
2015-10-23
2
-2
/
+4
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-15
2
-0
/
+2
*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-12
4
-15
/
+31
*
Several bug-fixed related to synthesis, library handling, and timimg info.
Alan Mishchenko
2015-09-23
1
-2
/
+4
*
Updating Mio to use int instead of float.
Alan Mishchenko
2015-08-31
2
-2
/
+192
*
Important bug fixes in standard-cell library handling and mapper &nf.
Alan Mishchenko
2015-08-28
1
-9
/
+27
*
Improving the criteria to select representative gates in 'map' with floating-...
Alan Mishchenko
2015-04-25
1
-47
/
+60
*
Adding platform-independent (alphabetic) way of sorting Genlib gates and sele...
Alan Mishchenko
2015-04-17
2
-20
/
+56
*
Adding APIs to retrieve NOR/OR gates from the library.
Alan Mishchenko
2015-04-14
4
-4
/
+15
*
Getting default AND-node delay from Genlib library.
Alan Mishchenko
2015-04-06
2
-0
/
+2
*
Fixed a typo in variable names.
Alan Mishchenko
2015-02-07
1
-9
/
+9
*
Major rehash of the CBA code.
Alan Mishchenko
2015-01-31
2
-0
/
+21
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-08
1
-0
/
+8
*
Recommended changes for portability.
Alan Mishchenko
2014-10-12
1
-1
/
+1
*
Suggested patch for type-punned warnings
Alan Mishchenko
2014-10-10
1
-3
/
+6
*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-26
1
-1
/
+1
*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-26
1
-0
/
+145
*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-25
6
-10
/
+163
*
Bug fix in technology mapper.
Alan Mishchenko
2013-11-24
1
-4
/
+13
*
Several changes to allow Liberty files without delay info.
Alan Mishchenko
2013-11-21
1
-0
/
+1
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-10-13
1
-1
/
+1
*
Integrating synthesis into the new BMC engine.
Alan Mishchenko
2013-10-02
1
-4
/
+3
*
Bug fixes in the library processing,.
Alan Mishchenko
2013-10-02
1
-6
/
+10
*
Unifying standard cell library representations.
Alan Mishchenko
2013-09-17
3
-5
/
+39
*
Infrastructure to support full Liberty format and unitification of library re...
Alan Mishchenko
2013-09-15
3
-3
/
+5
*
Improved gate-sizing.
Alan Mishchenko
2013-07-29
2
-0
/
+10
*
Tuning standard-cell mapping flow.
Alan Mishchenko
2013-07-24
2
-47
/
+69
*
Small changes to the printout in timing analysis.
Alan Mishchenko
2013-07-19
1
-1
/
+1
*
Modified SCL gate library to read/write gate formula.
Alan Mishchenko
2013-03-26
4
-2
/
+102
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