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* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-222-0/+3
* Maintenance and updates.Alan Mishchenko2017-09-242-3/+3
* Maintenance and updates.Alan Mishchenko2017-09-202-3/+7
* Maintenance and updates.Alan Mishchenko2017-09-181-0/+1
* Compiler warnings.Alan Mishchenko2017-07-223-4/+4
* Synchronizing various data-structures.Alan Mishchenko2017-07-042-7/+162
* Saturating floating point computation.Alan Mishchenko2017-07-011-3/+7
* Bug fixes by Clifford Wolf.Alan Mishchenko2017-01-081-0/+4
* Compiler warnings.Alan Mishchenko2017-01-071-1/+1
* Adding truth table occurrence counters for 'if -c'.Alan Mishchenko2016-08-083-0/+14
* Enabled progress bar in the 'if' mapper (warning).Alan Mishchenko2016-08-081-1/+1
* Enabled delay computation for the cut output using cut inputs.Alan Mishchenko2016-08-083-2/+52
* Enabled progress bar in the 'if' mapper.Alan Mishchenko2016-08-081-5/+5
* Adding one argument to the delay-estimation API used for exact synthesis.Alan Mishchenko2016-07-311-3/+3
* Infrastructure for using the results of exact SAT-based synthesis during mapp...Alan Mishchenko2016-07-291-3/+25
* Infrastructure for using the results of exact SAT-based synthesis during mapp...Alan Mishchenko2016-07-293-17/+33
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-271-0/+1
* Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...Alan Mishchenko2016-01-301-1/+1
* Compiler warnings.Alan Mishchenko2015-10-211-2/+2
* Moving BDD-based threshold function detection to the BDD part of the code.Alan Mishchenko2015-10-162-0/+9
* Two fixes in 'dsd_filter'.Alan Mishchenko2015-10-071-1/+1
* Bug fix in 'if -g' (incorrect use of a macro).Alan Mishchenko2015-10-071-3/+3
* Threshold logic checking code by Augusto Neutzling and Jody Matos.Alan Mishchenko2015-09-231-3/+6
* Experiments with mapping plus small changes.Alan Mishchenko2015-08-233-3/+10
* Small changes to enable collecting results using &ps -D file.Alan Mishchenko2015-07-092-0/+2
* Bug fix in programmable cell parser and minor tuning.Alan Mishchenko2015-07-081-1/+2
* C++ compiler typecast problem.Alan Mishchenko2015-07-081-1/+1
* Undo recent assert.Alan Mishchenko2015-06-271-2/+2
* Supporting AND-gate cuts in 'if' and '&if'Alan Mishchenko2015-06-213-6/+27
* Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.Alan Mishchenko2015-05-151-2/+7
* Making sure 0-input LUTs are supported by the DSD matching code.Alan Mishchenko2015-05-141-5/+5
* Support for representing programmable cell configuration data (bug fix).Alan Mishchenko2015-03-091-1/+4
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-1/+2
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-083-64/+222
* Experiments with SAT-based cube enumeration.Alan Mishchenko2015-03-051-3/+4
* Fixed a typo in variable names.Alan Mishchenko2015-02-071-2/+2
* New assertions and bug fix in DSD balancing.Alan Mishchenko2015-01-272-8/+11
* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-2/+3
* Bug fix in reading box library.Alan Mishchenko2014-12-201-1/+1
* Adding new mapping feature.Alan Mishchenko2014-12-114-18/+56
* Bug fix in truth table computation.Alan Mishchenko2014-10-151-11/+9
* MUX decomposition during mapping.Alan Mishchenko2014-10-111-1/+0
* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-1/+2
* Small changes.Alan Mishchenko2014-10-081-0/+2
* Compiler warnings.Alan Mishchenko2014-10-082-1/+3
* Detection of threshold functions.Alan Mishchenko2014-10-082-0/+74
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-2/+9
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-043-15/+126
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-032-0/+11
* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
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