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| * Adding command &reshape.Alan Mishchenko2021-09-212-21/+63
| * Removing unused command.Alan Mishchenko2021-09-212-157/+0
| * Various changes.Alan Mishchenko2021-09-213-13/+23
| * Improving MiniAIG and name manager.Alan Mishchenko2021-09-161-1/+1
| * Further debugging of MiniLUT APIs.Alan Mishchenko2021-09-161-0/+1
| * Various changes.Alan Mishchenko2021-09-141-9/+16
| * Enable command 'pipe' for pipelining.Alan Mishchenko2021-09-133-15/+15
| * Disabling command print_mint when CUDD is not used.Alan Mishchenko2021-09-071-0/+7
| * Bug fix in the timing manager.Alan Mishchenko2021-09-061-28/+30
| * Various changes.Alan Mishchenko2021-09-042-2/+2
| * Additional MiniLUT API.Alan Mishchenko2021-09-031-0/+1
| * Various changes.Alan Mishchenko2021-09-023-7/+278
| * Allow &mfs to work on sequential AIGs.Alan Mishchenko2021-08-241-1/+10
| * Compiler warnings.Alan Mishchenko2021-08-235-5/+7
| * Adding input/output/flop name reading in command &r.Alan Mishchenko2021-08-221-0/+39
| * Support of pair-wise miter and other changes.Alan Mishchenko2021-08-222-4/+21
| * Merge pull request #133 from twier/inv_get_name_mangling_fixalanminko2021-08-192-9/+43
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| | * Add comment to Wlc_NtkGetInv about vNamesIn's roleTobias Wiersema2021-08-191-0/+2
| | * Fix typo inifity -> infinity in inv_get helpTobias Wiersema2021-08-191-1/+1
| | * Add inv_get -f to read flop names from GIATobias Wiersema2021-08-192-8/+40
| * | Extending &trim to trim structurally equivalent primary outputs.Alan Mishchenko2021-08-191-3/+14
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| * Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-3/+8
| * Suggested changes to collect and pass timing information (unused variable).Alan Mishchenko2021-08-121-1/+1
| * Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-121-7/+5
| * Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-122-13/+64
| * Making &cec support the miter circuit.Alan Mishchenko2021-08-051-0/+14
| * Supporting simple operators in NDR.Alan Mishchenko2021-08-052-4/+4
| * Adding node ordering options to command &dfs.Alan Mishchenko2021-08-051-22/+13
| * Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-021-7/+3
| * Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-011-1/+2
| * Allow retiming to skip some logic.Alan Mishchenko2021-07-314-9/+69
| * Upgrading choice computation.Alan Mishchenko2021-07-312-21/+31
| * Experiments with cofactoring.Alan Mishchenko2021-07-311-6/+23
| * Experimental simulation commands.Alan Mishchenko2021-07-253-65/+458
| * Command to move CI/CO names.Alan Mishchenko2021-07-161-2/+3
| * Command to move CI/CO names.Alan Mishchenko2021-07-162-6/+235
| * Several unrelated changes.Alan Mishchenko2021-07-151-0/+67
| * Experiments with LUT mapping for small functions.Alan Mishchenko2021-07-131-3/+14
| * Experiments with CEC.Alan Mishchenko2021-07-101-4/+26
| * Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+55
| * Adding place holder file for resub experiments.Alan Mishchenko2021-06-241-6/+7
| * Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-192-28/+47
| * Experiments with cut computation.Alan Mishchenko2021-06-051-0/+1
| * Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
| * Updating LUT synthesis code.Alan Mishchenko2021-05-252-35/+120
| * Adding command &extract.Alan Mishchenko2021-05-182-1/+84
| * Updating LUT synthesis code.Alan Mishchenko2021-05-166-64/+439
| * Adding switch muxes -a to create networks of ADDs.Alan Mishchenko2021-05-153-14/+37
| * Updating LUT synthesis code.Alan Mishchenko2021-05-111-14/+25
| * Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-1110-19/+29
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