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* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-175-230/+488
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-165-78/+277
* New choice computation.Alan Mishchenko2014-09-161-10/+65
* Code restructuring.Alan Mishchenko2014-09-161-0/+49
* Compiler error (duplicate typedef).Alan Mishchenko2014-09-151-1/+0
* Compiler warnings.Alan Mishchenko2014-09-124-47/+47
* Replacing tabs with spaces.Alan Mishchenko2014-09-121-1/+1
* New word-level representation package.Alan Mishchenko2014-09-1212-61/+2214
* Resetting the random seed in 'sparsify'.Alan Mishchenko2014-09-111-0/+1
* Bug fix in transferring timing info.Alan Mishchenko2014-09-092-5/+62
* Added command 'move_names'.Alan Mishchenko2014-08-281-1/+1
* Added command 'move_names'.Alan Mishchenko2014-08-282-0/+106
* Tuning LUT mapping flow.Alan Mishchenko2014-08-281-0/+1
* Tuning LUT mapping flow.Alan Mishchenko2014-08-271-1/+1
* Compiler warning.Alan Mishchenko2014-08-271-2/+2
* Tuning LUT mapping flow.Alan Mishchenko2014-08-271-0/+135
* Improvements BLIF parser.Alan Mishchenko2014-08-273-4/+130
* Improvements to DSD balancing.Alan Mishchenko2014-08-274-37/+103
* Adding commands to save/load best network.Alan Mishchenko2014-08-262-7/+166
* Improving GIA interfaces for some procedures.Alan Mishchenko2014-08-251-1/+1
* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-251-0/+116
* Improving print-out of 'dsd -p'.Alan Mishchenko2014-08-221-1/+4
* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-201-7/+7
* Extended command &cone to extract timing critical cones.Alan Mishchenko2014-08-191-13/+51
* Added command 'sparsify' to derive ISF from CSF.Alan Mishchenko2014-08-182-0/+212
* Changing default CNF generation in &bmc.Alan Mishchenko2014-08-181-1/+1
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-1/+1
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-161-0/+2
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-162-1/+55
* Enabling circuit solver in &fraig.Alan Mishchenko2014-08-121-2/+6
* Bug fix in &fraig -L <num>.Alan Mishchenko2014-08-121-2/+2
* Bug fix in &fraig -L <num>.Alan Mishchenko2014-08-121-2/+2
* Adding delay optimization to synthesis script &syn2.Alan Mishchenko2014-08-081-15/+30
* Enabling cofactoring in the mapper.Alan Mishchenko2014-08-061-2/+22
* Enabling ISOP-based minimization in 'collapse' if EXDC is available.Alan Mishchenko2014-08-042-2/+35
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-021-0/+20
* Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, ...Alan Mishchenko2014-08-021-4/+26
* Small changes.Alan Mishchenko2014-07-292-3/+4
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-283-0/+119
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-261-0/+189
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-251-9/+14
* Bug fix in 'print_gates' due to the mix-up of the inverter.Alan Mishchenko2014-07-221-1/+1
* Small changes.Alan Mishchenko2014-07-211-7/+9
* Adding new command &sopb for resource-aware SOP balancing.Alan Mishchenko2014-07-211-34/+107
* Updates and changes to several packages.Alan Mishchenko2014-07-202-11/+41
* Small changes in several packages.Alan Mishchenko2014-07-171-1/+1
* Improvements to profiling and printing statistics.Alan Mishchenko2014-07-091-6/+16
* Improvements to false path detection.Alan Mishchenko2014-07-081-1/+1
* Improvements to representation of choices.Alan Mishchenko2014-07-011-3/+7
* Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_...Alan Mishchenko2014-06-301-14/+12
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