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Age
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*
Updated version of LMS code.
Alan Mishchenko
2012-09-26
1
-3
/
+3
*
Updated version of LMS code.
Alan Mishchenko
2012-09-26
1
-4
/
+6
*
Improvements to the NPN semi-canonical form computation package.
Alan Mishchenko
2012-09-25
1
-1
/
+1
*
Improvements to the NPN semi-canonical form computation package.
Alan Mishchenko
2012-09-25
2
-55
/
+88
*
Cleaned up interfaces of genlib/liberty/supergate reading/writing.
Alan Mishchenko
2012-09-25
2
-7
/
+23
*
Changed printouts in a few places in supergate computation.
Alan Mishchenko
2012-09-24
2
-1
/
+3
*
Testing GIA with time manager.
Alan Mishchenko
2012-09-24
1
-3
/
+3
*
Testing GIA with time manager.
Alan Mishchenko
2012-09-23
3
-38
/
+432
*
Modified structural constraint extraction (unfold -s) to work for multi-outpu...
Alan Mishchenko
2012-09-23
1
-2
/
+2
*
Migrating to array-based traversal ID.
Alan Mishchenko
2012-09-23
4
-77
/
+19
*
Cleaing AIG manager by removing pointers to HAIG.
Alan Mishchenko
2012-09-23
7
-199
/
+1
*
Integrating time manager into choice computation.
Alan Mishchenko
2012-09-22
1
-2
/
+4
*
Added simplification before the concurrent call to PDR.
Alan Mishchenko
2012-09-20
1
-2
/
+6
*
Added simplification before the concurrent call to PDR.
Alan Mishchenko
2012-09-20
1
-2
/
+2
*
Added slack computation to 'stime'.
Alan Mishchenko
2012-09-20
1
-0
/
+3
*
Modified 'read' to read all types of libraries (genlib, liberty, scl).
Alan Mishchenko
2012-09-20
1
-0
/
+2
*
Modified 'read' to read all types of libraries (genlib, liberty, scl).
Alan Mishchenko
2012-09-20
2
-2
/
+17
*
Fixes to Verilog parser.
Alan Mishchenko
2012-09-20
3
-3
/
+9
*
Extending Liberty parser to handle multi-output cells.
Alan Mishchenko
2012-09-19
1
-1
/
+1
*
Extending Liberty parser to handle multi-output cells.
Alan Mishchenko
2012-09-19
4
-9
/
+9
*
Extending Liberty parser to handle multi-output cells.
Alan Mishchenko
2012-09-19
5
-25
/
+45
*
Extending BLIF parser/write to hangle multi-output cells.
Alan Mishchenko
2012-09-19
7
-100
/
+235
*
Changes to command 'upsize'.
Alan Mishchenko
2012-09-18
1
-0
/
+3
*
Fixing mismatch between declaration of the output value of Extra_CpuTime.
Alan Mishchenko
2012-09-18
1
-3
/
+7
*
Added delay multipliers to 'map'.
Alan Mishchenko
2012-09-16
1
-7
/
+13
*
Added delay multipliers to 'map'.
Alan Mishchenko
2012-09-16
2
-17
/
+36
*
Changed a few things in the refinement package of &gla.
Alan Mishchenko
2012-09-16
1
-1
/
+1
*
Restructured the code to post-process object used during refinement in &gla.
Alan Mishchenko
2012-09-16
1
-11
/
+8
*
Cleaned 'abc.c' by removing useless procedures.
Alan Mishchenko
2012-09-15
1
-1689
/
+939
*
Created new abstraction package from the code that was all over the place.
Alan Mishchenko
2012-09-15
2
-470
/
+13
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
3
-15
/
+4
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-9
/
+12
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-2
/
+18
*
Scalable gate-level abstraction.
Alan Mishchenko
2012-09-11
1
-9
/
+30
*
Added -C to command line for running commands, then staying in interactive mode
Niklas Een
2012-09-11
1
-28
/
+39
*
Fixing Verilog writer's way of writing module names.
Alan Mishchenko
2012-09-11
1
-1
/
+1
*
Unified print-out of property failures produced by all engines.
Alan Mishchenko
2012-09-09
1
-5
/
+5
*
Added switch '-p' to '&gla -n' to use full proof for UNSAT core computation (...
Alan Mishchenko
2012-09-09
1
-2
/
+6
*
Started CEX minimization procedure.
Alan Mishchenko
2012-09-08
1
-0
/
+96
*
Updating &gla_refine to perform suffic refinement.
Alan Mishchenko
2012-09-07
1
-4
/
+17
*
Updating &gla_refine to perform suffic refinement.
Alan Mishchenko
2012-09-07
1
-5
/
+18
*
Integrated new fast semi-canonical form for Boolean functions up to 16 inputs.
Alan Mishchenko
2012-09-06
1
-2
/
+2
*
Integrated new fast semi-canonical form for Boolean functions up to 16 inputs.
Alan Mishchenko
2012-09-06
4
-28
/
+70
*
Added switch 'dch -r' to skip choices with structural support redundancy.
Alan Mishchenko
2012-09-05
1
-2
/
+6
*
Added error message when the user is trying 'dsat' for multi-output comb miters.
Alan Mishchenko
2012-09-05
1
-2
/
+2
*
Added new command &gla_shrink.
Alan Mishchenko
2012-09-04
2
-2
/
+95
*
Better batch mode printout.
Alan Mishchenko
2012-09-04
1
-1
/
+1
*
Enabled recording the name of the file GIA is coming from.
Alan Mishchenko
2012-09-04
2
-0
/
+3
*
Added switch &srm -A <file> for dumping SRM into a user-specified file.
Alan Mishchenko
2012-09-02
1
-10
/
+21
*
Fixing the way constants are written into mapped Verilog files.
Alan Mishchenko
2012-08-31
1
-0
/
+5
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