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* Enabling user-specified output signature in &polyn.Alan Mishchenko2018-06-131-6/+32
* Experiments with path enumeration.Alan Mishchenko2018-06-101-2/+60
* Compiler warnings.Alan Mishchenko2018-06-082-2/+2
* Improvements in bit-blasting of adders and multipliers.Alan Mishchenko2018-06-081-8/+200
* Adding switch 'clp -o' to reverse initial variable ordering.Alan Mishchenko2018-06-0717-36/+41
* Experiments with path enumeration.Alan Mishchenko2018-06-061-1/+1
* Supporting the decoder primitive in NDR and bit-blasting.Alan Mishchenko2018-06-056-4/+68
* Exposing a switch to generate carry-lookahead adder during bit-blasting.Alan Mishchenko2018-06-053-15/+60
* Adding command print_mint.Alan Mishchenko2018-06-041-0/+64
* Supporting SEL in bit-blasting.Alan Mishchenko2018-05-251-2/+22
* Supporting NMUX and SEL in NDR.Alan Mishchenko2018-05-244-2/+33
* Simple BDD package.Alan Mishchenko2018-05-231-1/+3
* Bug fix in supporting signed multiplication in NDR.Alan Mishchenko2018-05-181-6/+7
* Supporting wide MUX in NDR.Alan Mishchenko2018-05-161-2/+7
* Bug fix in the naming of outputs in %blast -d.Alan Mishchenko2018-05-101-3/+21
* Bug fix in &sat -x.Alan Mishchenko2018-05-071-2/+3
* Adding &sat -x to save CEXes for multi-output combinational miters.Alan Mishchenko2018-05-061-4/+33
* Updates to NDR format (bug fixes).Alan Mishchenko2018-05-032-11/+10
* Updates to NDR format (flops, memories, signed mult, etc).Alan Mishchenko2018-04-298-39/+352
* The ECO code (fix to the broken build).Alan Mishchenko2018-04-281-2/+2
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-2/+9
* The ECO code.Alan Mishchenko2018-04-251-2/+11
* The ECO code.Alan Mishchenko2018-04-252-8/+2500
* Typo in the command description.Alan Mishchenko2018-04-251-5/+5
* Memory abstraction.Alan Mishchenko2018-04-204-10/+20
* Memory abstraction.Alan Mishchenko2018-04-194-154/+284
* Memory abstraction.Alan Mishchenko2018-04-158-84/+1086
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-2/+2
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-8/+20
* Adding new NPN code developed by XueGong Zhou at Fudan University.Alan Mishchenko2018-03-252-7/+29
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-221-5/+14
* Temporary bug fix for signal names in WLC (correction).Alan Mishchenko2018-03-211-2/+5
* Temporary bug fix for signal names in WLC.Alan Mishchenko2018-03-211-0/+2
* Bug fix in blasting with boxes.Alan Mishchenko2018-03-061-1/+1
* Extending primitives supported by WLC.Alan Mishchenko2018-03-033-5/+85
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-286-1/+20
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-289-98/+296
* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-244-5/+15
* Bug fix in NDR handling.Alan Mishchenko2018-02-201-6/+38
* Compilation problem with pow().Alan Mishchenko2018-02-192-2/+2
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+1
* Experiments with LUT mapping.Alan Mishchenko2018-02-101-5/+18
* Fixing input swapping issue in MUXes derived from NDR.Alan Mishchenko2018-02-072-0/+4
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+1
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-053-19/+21
* Adding support of reading and writing designs using a new internal format (bu...Alan Mishchenko2018-01-291-18/+76
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-284-4/+362
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-4/+15
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+1
* Updates to exact synthesis commands.Alan Mishchenko2018-01-191-4/+26
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