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* Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, ...Alan Mishchenko2014-08-021-4/+26
* Small changes.Alan Mishchenko2014-07-292-3/+4
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-283-0/+119
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-261-0/+189
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-251-9/+14
* Bug fix in 'print_gates' due to the mix-up of the inverter.Alan Mishchenko2014-07-221-1/+1
* Small changes.Alan Mishchenko2014-07-211-7/+9
* Adding new command &sopb for resource-aware SOP balancing.Alan Mishchenko2014-07-211-34/+107
* Updates and changes to several packages.Alan Mishchenko2014-07-202-11/+41
* Small changes in several packages.Alan Mishchenko2014-07-171-1/+1
* Improvements to profiling and printing statistics.Alan Mishchenko2014-07-091-6/+16
* Improvements to false path detection.Alan Mishchenko2014-07-081-1/+1
* Improvements to representation of choices.Alan Mishchenko2014-07-011-3/+7
* Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_...Alan Mishchenko2014-06-301-14/+12
* Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_...Alan Mishchenko2014-06-301-10/+14
* Changes and improvements to different packages.Alan Mishchenko2014-06-281-1/+1
* Changes and improvements to different packages.Alan Mishchenko2014-06-281-6/+16
* Changes and improvements to different packages.Alan Mishchenko2014-06-261-0/+3
* Improvements to power-aware mapping.Alan Mishchenko2014-06-232-8/+17
* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-233-12/+55
* Added command &mux_profile.Alan Mishchenko2014-06-221-0/+43
* Experiments with balancing.Alan Mishchenko2014-06-221-0/+80
* New tools for profiling verification miters.Alan Mishchenko2014-06-201-2/+62
* Added quick GIG parser.Alan Mishchenko2014-06-191-0/+59
* Added delay-oriented balancing to unmapping in &st.Alan Mishchenko2014-06-191-1/+14
* Various changes to enable better CNF generation.Alan Mishchenko2014-06-171-0/+193
* Bug fix in writing latch init values in 'write_aiger'.Alan Mishchenko2014-06-171-3/+3
* Added transformation of CEX after 'fix_aig' and checking of transformed CEXes...Alan Mishchenko2014-06-172-24/+89
* Bug fix in CEC generation after rarity simulation and few small changes.Alan Mishchenko2014-06-161-5/+9
* Adding support of multi-output problems in &splitprove.Alan Mishchenko2014-06-151-1/+25
* Updates and bug fixes.Alan Mishchenko2014-06-151-2/+14
* Adding more features to the synthesis script &syn2.Alan Mishchenko2014-06-141-7/+35
* Specializing some truth-table functions to 6 inputs.Alan Mishchenko2014-06-141-20/+15
* Various modifications.Alan Mishchenko2014-06-121-22/+47
* Enabling switching activity.Alan Mishchenko2014-06-121-2/+6
* Integrating recent changes.Alan Mishchenko2014-06-121-36/+22
* Adding switch to &st to convert to larger gates.Alan Mishchenko2014-06-111-5/+12
* Various modifications.Alan Mishchenko2014-06-101-2/+174
* Skip 'scorr' when the network has no primary inputs.Alan Mishchenko2014-06-091-0/+6
* Adding print-out to &splitprove to see impact of cof variable on AIG size.Alan Mishchenko2014-06-071-5/+9
* Adding print-out to &splitprove to see impact of cof variable on AIG size.Alan Mishchenko2014-06-073-13/+24
* Adding a feature to collapse hierarhical AIGs.Alan Mishchenko2014-06-051-4/+17
* Correcting switching activity computation.Alan Mishchenko2014-06-052-41/+34
* Fixed printout of in the hierarchy log file.Alan Mishchenko2014-06-051-1/+1
* Fixed printout of in the hierarchy log file.Alan Mishchenko2014-06-051-2/+4
* Fixed printout of in the hierarchy log file.Alan Mishchenko2014-06-051-1/+1
* Fixed printout of in the hierarchy log file.Alan Mishchenko2014-06-051-1/+1
* ciJiang Long2014-06-041-1/+1
* the latest versionJiang Long2014-06-043-6/+72
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