summaryrefslogtreecommitdiffstats
path: root/src/base
Commit message (Collapse)AuthorAgeFilesLines
* The ECO code (fix to the broken build).Alan Mishchenko2018-04-281-2/+2
|
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-2/+9
|
* The ECO code.Alan Mishchenko2018-04-251-2/+11
|
* The ECO code.Alan Mishchenko2018-04-252-8/+2500
|
* Typo in the command description.Alan Mishchenko2018-04-251-5/+5
|
* Memory abstraction.Alan Mishchenko2018-04-204-10/+20
|
* Memory abstraction.Alan Mishchenko2018-04-194-154/+284
|
* Memory abstraction.Alan Mishchenko2018-04-158-84/+1086
|
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-2/+2
|
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-8/+20
|
* Adding new NPN code developed by XueGong Zhou at Fudan University.Alan Mishchenko2018-03-252-7/+29
|
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-221-5/+14
|
* Temporary bug fix for signal names in WLC (correction).Alan Mishchenko2018-03-211-2/+5
|
* Temporary bug fix for signal names in WLC.Alan Mishchenko2018-03-211-0/+2
|
* Bug fix in blasting with boxes.Alan Mishchenko2018-03-061-1/+1
|
* Extending primitives supported by WLC.Alan Mishchenko2018-03-033-5/+85
|
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-286-1/+20
|
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-289-98/+296
|
* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-244-5/+15
|
* Bug fix in NDR handling.Alan Mishchenko2018-02-201-6/+38
|
* Compilation problem with pow().Alan Mishchenko2018-02-192-2/+2
|
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+1
|
* Experiments with LUT mapping.Alan Mishchenko2018-02-101-5/+18
|
* Fixing input swapping issue in MUXes derived from NDR.Alan Mishchenko2018-02-072-0/+4
|
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+1
|
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-053-19/+21
|
* Adding support of reading and writing designs using a new internal format ↵Alan Mishchenko2018-01-291-18/+76
| | | | (bug fix).
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-284-4/+362
|
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-4/+15
|
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+1
|
* Updates to exact synthesis commands.Alan Mishchenko2018-01-191-4/+26
|
* New command 'testexact'.Alan Mishchenko2018-01-041-0/+51
|
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-301-2/+2
|
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-1/+170
|
* Bug fix in 'write_aiger_cex'.Alan Mishchenko2017-12-201-0/+1
|
* Adding parameter structure to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-59/+71
|
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-0/+27
|
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-2/+2
|
* Switch -a to use only AND-gates in 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-14/+22
|
* New command 'lutexact'.Alan Mishchenko2017-12-051-0/+104
|
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ↵Alan Mishchenko2017-12-035-17/+30
| | | | MUXes.
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-031-5/+0
|
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-2/+2
|
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-1/+6
|
* C++ comaptibility: add namespace support to GlucoseBaruch Sterin2017-11-231-0/+2
|
* C++ compatibility: fix bad pointer comparisonBaruch Sterin2017-11-231-1/+1
|
* Changes to make GIA structural hashing use a dedicated array instead of ↵Alan Mishchenko2017-11-131-2/+2
| | | | pObj->Value.
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+61
|
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-225-2/+10
|
* Adding random search in exact synthesis.Alan Mishchenko2017-10-201-6/+23
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 11:29:37 +0000