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* Experiments with arithmetic circuits.Alan Mishchenko2016-04-281-4/+4
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-272-3/+5
* Extending &satlut to work for 6-LUTs.Alan Mishchenko2016-04-271-5/+6
* Adding missing code to 'dress'.Alan Mishchenko2016-04-271-0/+65
* Bug fix in bit-blasting of remainder.Alan Mishchenko2016-04-261-1/+1
* Improved algo for edge computation.Alan Mishchenko2016-04-241-5/+0
* Adding new switch 'bdd -s' to translate SOP directly into BDD.Alan Mishchenko2016-04-241-3/+9
* Improved algo for edge computation.Alan Mishchenko2016-04-231-6/+2
* Improved algo for edge computation.Alan Mishchenko2016-04-221-2/+20
* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-131-12/+43
* Bug fix: change in the ordering of the reset flop (should be last, not first).Alan Mishchenko2016-04-131-2/+2
* Updates to Exorcism packageAlan Mishchenko2016-04-111-6/+4
* Updates to Exorcism packageAlan Mishchenko2016-04-111-1/+1
* Updates to Exorcism packageAlan Mishchenko2016-04-112-19/+18
* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG...Alan Mishchenko2016-04-1114-23/+3844
* Supporting edge information during mapping.Alan Mishchenko2016-04-111-5/+22
* Command &esop to convert AIG into ESOP.Alan Mishchenko2016-04-091-0/+49
* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-3/+0
* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-3/+13
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-2/+2
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+5
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-6/+67
* Supporting edge information during mapping.Alan Mishchenko2016-04-061-2/+5
* Supporting negative and reverse ranges of word-level variables in Wlc.Alan Mishchenko2016-04-046-106/+168
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-2/+7
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-7/+12
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-5/+15
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-031-8/+27
* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-031-5/+10
* Allowing Cba manager to be derived from another Cba manager.Alan Mishchenko2016-04-022-3/+3
* Windowing for technology mapping.Alan Mishchenko2016-03-302-7/+10
* Bug fix in truth table reading for funcs with less than 6 vars.Alan Mishchenko2016-03-282-2/+2
* Sorting multiplier inputs based on the number of constant bits.Alan Mishchenko2016-03-241-0/+21
* Typo in operator in Wlc_Ntk_t.Alan Mishchenko2016-03-181-1/+1
* Supporting bit-wise XNOR operator in Wlc_Ntk_t.Alan Mishchenko2016-03-185-3/+9
* Supporting complemented reduction operators.Alan Mishchenko2016-03-111-6/+7
* Supporting complemented reduction operators.Alan Mishchenko2016-03-105-11/+40
* Change error to warning in 'scorr'.Alan Mishchenko2016-03-091-2/+2
* Supporting ~^ as equality operator in Wlc.Alan Mishchenko2016-03-041-2/+3
* New hierarchical TT NPN matching.Alan Mishchenko2016-02-262-3/+26
* Improving bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-132-16/+46
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-131-0/+79
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-125-2/+97
* Experiments with SAT-based mapping.Alan Mishchenko2016-02-081-1/+1
* Added recursive bit-blasting of a carry-lookahead adder.Alan Mishchenko2016-02-061-0/+51
* Preserving internal signal names when 'strash' is not used.Alan Mishchenko2016-02-032-0/+7
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-1/+1
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-6/+13
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-024-11/+26
* An add-on to write Verilog for circuits mapped into simple gates.Alan Mishchenko2016-02-011-9/+22
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