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iCE40/abc
yosys-experimental
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Author
Age
Files
Lines
*
Tuning the flow scripts.
Alan Mishchenko
2014-09-20
1
-17
/
+75
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-19
1
-22
/
+20
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-18
1
-4
/
+4
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-18
1
-14
/
+28
*
Improving DSD manager.
Alan Mishchenko
2014-09-18
1
-6
/
+20
*
Concurrency for Boolean matching.
Alan Mishchenko
2014-09-18
3
-13
/
+47
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-17
1
-4
/
+29
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
2
-3
/
+4
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
5
-230
/
+488
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-16
5
-78
/
+277
*
New choice computation.
Alan Mishchenko
2014-09-16
1
-10
/
+65
*
Code restructuring.
Alan Mishchenko
2014-09-16
1
-0
/
+49
*
Compiler error (duplicate typedef).
Alan Mishchenko
2014-09-15
1
-1
/
+0
*
Compiler warnings.
Alan Mishchenko
2014-09-12
4
-47
/
+47
*
Replacing tabs with spaces.
Alan Mishchenko
2014-09-12
1
-1
/
+1
*
New word-level representation package.
Alan Mishchenko
2014-09-12
12
-61
/
+2214
*
Resetting the random seed in 'sparsify'.
Alan Mishchenko
2014-09-11
1
-0
/
+1
*
Bug fix in transferring timing info.
Alan Mishchenko
2014-09-09
2
-5
/
+62
*
Added command 'move_names'.
Alan Mishchenko
2014-08-28
1
-1
/
+1
*
Added command 'move_names'.
Alan Mishchenko
2014-08-28
2
-0
/
+106
*
Tuning LUT mapping flow.
Alan Mishchenko
2014-08-28
1
-0
/
+1
*
Tuning LUT mapping flow.
Alan Mishchenko
2014-08-27
1
-1
/
+1
*
Compiler warning.
Alan Mishchenko
2014-08-27
1
-2
/
+2
*
Tuning LUT mapping flow.
Alan Mishchenko
2014-08-27
1
-0
/
+135
*
Improvements BLIF parser.
Alan Mishchenko
2014-08-27
3
-4
/
+130
*
Improvements to DSD balancing.
Alan Mishchenko
2014-08-27
4
-37
/
+103
*
Adding commands to save/load best network.
Alan Mishchenko
2014-08-26
2
-7
/
+166
*
Improving GIA interfaces for some procedures.
Alan Mishchenko
2014-08-25
1
-1
/
+1
*
Correcting incorrect handling of timing in several &-commands.
Alan Mishchenko
2014-08-25
1
-0
/
+116
*
Improving print-out of 'dsd -p'.
Alan Mishchenko
2014-08-22
1
-1
/
+4
*
Propagating timing support to the new synthesis/mapping commands.
Alan Mishchenko
2014-08-20
1
-7
/
+7
*
Extended command &cone to extract timing critical cones.
Alan Mishchenko
2014-08-19
1
-13
/
+51
*
Added command 'sparsify' to derive ISF from CSF.
Alan Mishchenko
2014-08-18
2
-0
/
+212
*
Changing default CNF generation in &bmc.
Alan Mishchenko
2014-08-18
1
-1
/
+1
*
Added DSD-based collapsing &dsd.
Alan Mishchenko
2014-08-16
1
-1
/
+1
*
Adding specialized matching to 'if'.
Alan Mishchenko
2014-08-16
1
-0
/
+2
*
Added DSD-based collapsing &dsd.
Alan Mishchenko
2014-08-16
2
-1
/
+55
*
Enabling circuit solver in &fraig.
Alan Mishchenko
2014-08-12
1
-2
/
+6
*
Bug fix in &fraig -L <num>.
Alan Mishchenko
2014-08-12
1
-2
/
+2
*
Bug fix in &fraig -L <num>.
Alan Mishchenko
2014-08-12
1
-2
/
+2
*
Adding delay optimization to synthesis script &syn2.
Alan Mishchenko
2014-08-08
1
-15
/
+30
*
Enabling cofactoring in the mapper.
Alan Mishchenko
2014-08-06
1
-2
/
+22
*
Enabling ISOP-based minimization in 'collapse' if EXDC is available.
Alan Mishchenko
2014-08-04
2
-2
/
+35
*
Profiling code for SOP/DSD/LMS balancing.
Alan Mishchenko
2014-08-02
1
-0
/
+20
*
Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, ...
Alan Mishchenko
2014-08-02
1
-4
/
+26
*
Small changes.
Alan Mishchenko
2014-07-29
2
-3
/
+4
*
Adding support for standard-cell mapping.
Alan Mishchenko
2014-07-28
3
-0
/
+119
*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-26
1
-0
/
+189
*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-25
1
-9
/
+14
*
Bug fix in 'print_gates' due to the mix-up of the inverter.
Alan Mishchenko
2014-07-22
1
-1
/
+1
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