iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Integrating barrier buffers.	Alan Mishchenko	2014-12-08	1	-1/+1
*	Added and verified bit-blasting of power operator.	Alan Mishchenko	2014-11-30	1	-0/+32
*	Induced bug fix in bitblasting of rotation operator.	Alan Mishchenko	2014-11-29	1	-1/+2
*	Merging two branches.	Alan Mishchenko	2014-11-17	2	-1/+3
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\| *	Bug fix in abstracting boxes.	Alan Mishchenko	2014-11-17	2	-1/+3
* \|	AND/OR bug in the UIF computation.	Alan Mishchenko	2014-11-17	1	-1/+1
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*	Improvements to word-level network package.	Alan Mishchenko	2014-11-14	1	-2/+2
*	Improvements to word-level network package.	Alan Mishchenko	2014-11-14	1	-2/+2
*	Improvements to word-level network package.	Alan Mishchenko	2014-11-14	8	-128/+472
*	Enabling AIGs with boxes for word-level and sequential designs.	Alan Mishchenko	2014-11-14	1	-4/+5
*	Enabling AIGs with boxes for word-level and sequential designs.	Alan Mishchenko	2014-11-13	5	-16/+151
*	Bug fix in blasting MUX with different ranges of inputs and the output.	Alan Mishchenko	2014-11-10	1	-2/+2
*	Improvements to the parser.	Alan Mishchenko	2014-10-10	1	-7/+86
*	Bug fix in the bit-blaster.	Alan Mishchenko	2014-10-10	1	-3/+3
*	Bug fix in Verilog writer.	Alan Mishchenko	2014-10-02	1	-8/+8
*	Improvements to bit-blaster.	Alan Mishchenko	2014-10-01	2	-23/+88
*	Improvements to bit-blaster.	Alan Mishchenko	2014-09-30	1	-1/+1
*	Improvements to bit-blaster.	Alan Mishchenko	2014-09-30	2	-73/+117
*	Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).	Alan Mishchenko	2014-09-28	1	-1/+1
*	Support for sequential designs in word-level Verilog.	Alan Mishchenko	2014-09-26	5	-79/+196
*	Enabling print-out, for each operator, of the percetage of AND nodes after bi...	Alan Mishchenko	2014-09-25	4	-14/+35
*	Printing node type statistics.	Alan Mishchenko	2014-09-24	1	-33/+57
*	Printing node type statistics.	Alan Mishchenko	2014-09-24	1	-10/+10
*	Printing node type statistics.	Alan Mishchenko	2014-09-24	2	-2/+106
*	Bug fix in handling MUXes in Verilog parser, induced by recent changes.	Alan Mishchenko	2014-09-24	1	-0/+2
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	1	-2/+2
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	3	-18/+167
*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-1/+15
*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-7/+27
*	Concurrency for Boolean matching.	Alan Mishchenko	2014-09-18	1	-1/+1
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	2	-3/+4
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	5	-230/+488
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-16	5	-78/+277
*	Compiler error (duplicate typedef).	Alan Mishchenko	2014-09-15	1	-1/+0
*	Compiler warnings.	Alan Mishchenko	2014-09-12	4	-47/+47
*	New word-level representation package.	Alan Mishchenko	2014-09-12	8	-0/+2203