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path: root/src/base/wlc/wlcNtk.c
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* Improving SMT-LIB parser.Alan Mishchenko2016-05-231-7/+12
* Improving SMT-LIB parser.Alan Mishchenko2016-05-211-34/+37
* Improving SMT-LIB parser.Alan Mishchenko2016-05-201-0/+6
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-0/+5
* Supporting negative and reverse ranges of word-level variables in Wlc.Alan Mishchenko2016-04-041-39/+44
* Typo in operator in Wlc_Ntk_t.Alan Mishchenko2016-03-181-1/+1
* Supporting bit-wise XNOR operator in Wlc_Ntk_t.Alan Mishchenko2016-03-181-0/+3
* Supporting complemented reduction operators.Alan Mishchenko2016-03-101-0/+9
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-121-0/+2
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-0/+1
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+1
* Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling ...Alan Mishchenko2015-07-161-7/+92
* Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator ...Alan Mishchenko2015-07-141-2/+4
* Bug fixing in %blast when blasting mod operator (handling zero divisor).Alan Mishchenko2015-07-071-0/+2
* Adding new debugging feature to Wlc_Ntk_t.Alan Mishchenko2015-06-191-0/+53
* Sequential word-level simulator for Wlc_Ntk_t.Alan Mishchenko2015-06-041-0/+1
* Fix inconsistency between operators and symbols in Wlc_Ntk_t.Alan Mishchenko2015-04-251-18/+19
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-181-46/+0
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-151-0/+47
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-111-1/+1
* Added SMT parser for Wlc_Ntk_t.Alan Mishchenko2015-02-071-0/+2
* Outputting initial state in Wlc_Ntk_t.Alan Mishchenko2015-01-251-1/+2
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-1/+4
* Improvements to word-level network package.Alan Mishchenko2014-11-141-2/+2
* Improvements to word-level network package.Alan Mishchenko2014-11-141-31/+24
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-0/+24
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-1/+6
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-261-28/+33
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-251-10/+19
* Printing node type statistics.Alan Mishchenko2014-09-241-33/+57
* Printing node type statistics.Alan Mishchenko2014-09-241-10/+10
* Printing node type statistics.Alan Mishchenko2014-09-241-2/+104
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-171-28/+31
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-161-4/+11
* Compiler warnings.Alan Mishchenko2014-09-121-0/+44
* New word-level representation package.Alan Mishchenko2014-09-121-0/+283
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