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path: root/src/base/wlc/wlcBlast.c
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* Changes to PDR to compute f-inf clauses and import invariant (or clauses) as ...Alan Mishchenko2016-01-141-46/+0
* Adding names to GIA inputs/outputs (addressing x-valued flops).Alan Mishchenko2015-12-221-1/+51
* Adding names to GIA inputs/outputs. Changing polarity of invariant generated...Alan Mishchenko2015-12-211-0/+34
* New command %psinv.Alan Mishchenko2015-11-231-0/+45
* Adding support for black boxes in extended AIG.Alan Mishchenko2015-10-041-1/+1
* Improving bit-blasting of full-adder.Alan Mishchenko2015-09-231-5/+19
* Alternative way to bit-blast a divisor.Alan Mishchenko2015-08-291-4/+39
* Updates to Cba data-structure.Alan Mishchenko2015-07-231-0/+4
* Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator ...Alan Mishchenko2015-07-141-49/+127
* Improved bit-blasting of adders and multipliers in Wlc_Ntk_t.Alan Mishchenko2015-07-131-3/+46
* Bug fixing in %blast when blasting MUX coming from always-statement.Alan Mishchenko2015-07-071-3/+22
* Bug fixing in %blast when blasting mod operator (handling zero divisor).Alan Mishchenko2015-07-071-1/+2
* Bug with in signed MUX.Alan Mishchenko2015-06-141-8/+11
* Bug with in signed MUX.Alan Mishchenko2015-06-121-2/+4
* Sequential word-level simulator for Wlc_Ntk_t.Alan Mishchenko2015-06-041-4/+7
* Improvements to the SMTLIB parser.Alan Mishchenko2015-02-281-0/+4
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-151-0/+8
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-1/+1
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-0/+14
* Integrating barrier buffers.Alan Mishchenko2014-12-081-1/+1
* Added and verified bit-blasting of power operator.Alan Mishchenko2014-11-301-0/+32
* Improvements to word-level network package.Alan Mishchenko2014-11-141-16/+16
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-141-4/+5
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-10/+106
* Bug fix in blasting MUX with different ranges of inputs and the output.Alan Mishchenko2014-11-101-2/+2
* Bug fix in the bit-blaster.Alan Mishchenko2014-10-101-3/+3
* Improvements to bit-blaster.Alan Mishchenko2014-10-011-14/+42
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-1/+1
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-72/+111
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-261-14/+23
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-251-0/+6
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-16/+48
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-1/+15
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-7/+27
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-171-119/+282
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-161-0/+6
* Compiler warnings.Alan Mishchenko2014-09-121-1/+1
* New word-level representation package.Alan Mishchenko2014-09-121-0/+363
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