iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.	Alan Mishchenko	2015-01-21	1	-1/+1
*	Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.	Alan Mishchenko	2015-01-21	1	-0/+14
*	Integrating barrier buffers.	Alan Mishchenko	2014-12-08	1	-1/+1
*	Added and verified bit-blasting of power operator.	Alan Mishchenko	2014-11-30	1	-0/+32
*	Improvements to word-level network package.	Alan Mishchenko	2014-11-14	1	-16/+16
*	Enabling AIGs with boxes for word-level and sequential designs.	Alan Mishchenko	2014-11-14	1	-4/+5
*	Enabling AIGs with boxes for word-level and sequential designs.	Alan Mishchenko	2014-11-13	1	-10/+106
*	Bug fix in blasting MUX with different ranges of inputs and the output.	Alan Mishchenko	2014-11-10	1	-2/+2
*	Bug fix in the bit-blaster.	Alan Mishchenko	2014-10-10	1	-3/+3
*	Improvements to bit-blaster.	Alan Mishchenko	2014-10-01	1	-14/+42
*	Improvements to bit-blaster.	Alan Mishchenko	2014-09-30	1	-1/+1
*	Improvements to bit-blaster.	Alan Mishchenko	2014-09-30	1	-72/+111
*	Support for sequential designs in word-level Verilog.	Alan Mishchenko	2014-09-26	1	-14/+23
*	Enabling print-out, for each operator, of the percetage of AND nodes after bi...	Alan Mishchenko	2014-09-25	1	-0/+6
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	1	-2/+2
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	1	-16/+48
*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-1/+15
*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-7/+27
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	1	-119/+282
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-16	1	-0/+6
*	Compiler warnings.	Alan Mishchenko	2014-09-12	1	-1/+1
*	New word-level representation package.	Alan Mishchenko	2014-09-12	1	-0/+363