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* Bug fix in parsing hierarchical BLIF with mapping.Alan Mishchenko2019-11-181-3/+16
* Fix read_bench to read standard gate names in lower-case.Alan Mishchenko2019-08-281-9/+9
* Adding synonym of 'read_dsd'.Alan Mishchenko2019-06-201-0/+1
* Modifying 'write_truth' to dump truth table in hex.Alan Mishchenko2019-05-071-3/+11
* Adding switch 'read_truth -f <file_name>' to read truth table from file.Alan Mishchenko2019-04-151-9/+22
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-053-4/+4
* Suggested white-space changes for fewer gcc warnings.Alan Mishchenko2019-03-041-1/+1
* Add skip feature to CEX printing.Alan Mishchenko2019-02-081-1/+9
* Exploring other ways of CEX writing.Alan Mishchenko2019-01-211-5/+51
* Undoing some recent changes for improved CEX writing.Alan Mishchenko2019-01-211-65/+8
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-181-12/+28
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-171-19/+37
* Fixing the problem with outputting word-level CEXes.Alan Mishchenko2019-01-161-1/+24
* Various usability changes.Alan Mishchenko2018-11-181-3/+14
* Adding switch to 'write_pla' to write random onset minterms of the first PO f...Alan Mishchenko2018-09-291-2/+8
* Adding switch to 'write_pla' to write random onset minterms of the first PO f...Alan Mishchenko2018-09-282-10/+154
* Adding switch 'clp -o' to reverse initial variable ordering.Alan Mishchenko2018-06-071-1/+1
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-2/+2
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-8/+20
* Bug fix in 'write_aiger_cex'.Alan Mishchenko2017-12-201-0/+1
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-034-16/+29
* Fixing minimize_assuptions using Glucose.Alan Mishchenko2017-10-021-0/+1
* Maintenance and updates.Alan Mishchenko2017-09-241-1/+1
* Compiler warnings.Alan Mishchenko2017-07-221-2/+2
* Adding PDR with abstraction.Alan Mishchenko2017-02-101-1/+1
* Improving CEX minimization.Alan Mishchenko2017-02-101-1/+1
* Improvements in AIG visualization.Alan Mishchenko2017-02-051-2/+2
* Updates to arithmetic verification.Alan Mishchenko2017-01-301-1/+1
* Commenting out bailout in 'print_cex' when CEX has latches initialized to 1.Alan Mishchenko2016-11-301-1/+2
* New SAT-based optimization package.Alan Mishchenko2016-11-261-1/+1
* Parser for JSON format.Alan Mishchenko2016-10-254-2/+391
* Unsuccessful attempt to improve quality of factoring by limiting distance-1 m...Alan Mishchenko2016-08-061-12/+67
* Extension in the detection code.Alan Mishchenko2016-07-191-0/+2
* New multi-output PLA reader and preprocessor (read_plamo) (updated dist-1 mer...Alan Mishchenko2016-06-171-2/+54
* New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge).Alan Mishchenko2016-06-162-83/+355
* Change to BENCH reader to read DFF with four inputs.Alan Mishchenko2016-06-161-7/+30
* New multi-output PLA reader and preprocessor (read_plamo).Alan Mishchenko2016-06-163-0/+491
* Detecting properties of internal nodes.Alan Mishchenko2016-06-121-0/+58
* Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset).Alan Mishchenko2016-05-124-15/+30
* Updating GIG parser.Alan Mishchenko2016-05-011-1/+1
* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG...Alan Mishchenko2016-04-114-12/+17
* An add-on to write Verilog for circuits mapped into simple gates.Alan Mishchenko2016-02-011-9/+22
* Changing 'refactor' to work with truth tables.Alan Mishchenko2015-08-251-7/+0
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+7
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+10
* Improvements to Cba data-structure.Alan Mishchenko2015-07-291-4/+4
* Improvements to Cba data-structure.Alan Mishchenko2015-07-281-2/+2
* Several additional fixed in the timing manager.Alan Mishchenko2015-04-072-2/+14
* Improvements in reading timing information from BLIF.Alan Mishchenko2015-04-051-18/+127
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