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* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-9/+35
* Added quick GIG parser.Alan Mishchenko2014-06-191-0/+59
* Bug fix in writing latch init values in 'write_aiger'.Alan Mishchenko2014-06-171-3/+3
* Fix PLA reader to correctly report error file numbers.Alan Mishchenko2014-06-021-5/+6
* add an option to write_cex to write the CEX in AIGER 1.9 format.Baruch Sterin2014-05-121-1/+11
* Added dumping original object names into a file.Alan Mishchenko2014-04-261-2/+12
* Renamed Abc_Lib_t into Abc_Des_t and removed some dead code.Alan Mishchenko2014-04-093-249/+17
* Better CEX minimization and renaming of write_counter into write_cex.Alan Mishchenko2014-04-041-12/+27
* Adding functionally observable fault testing.Alan Mishchenko2014-03-311-2/+5
* Improving network visualization in show/&show.Alan Mishchenko2014-03-281-2/+26
* Adding barrier buffers.Alan Mishchenko2014-03-183-11/+33
* Adding barrier buffers.Alan Mishchenko2014-03-163-21/+51
* Changes to LUT mappers.Alan Mishchenko2014-03-091-0/+4
* Adding check for the presence of precomputed data.Alan Mishchenko2013-12-291-0/+5
* New command &write_cnf.Alan Mishchenko2013-12-181-0/+66
* Bug fixes in the above patches.Alan Mishchenko2013-12-031-4/+4
* Suggested patch of AIG writers.Alan Mishchenko2013-12-031-30/+106
* Bug fix in writing constants in write_verilog.Alan Mishchenko2013-11-211-1/+1
* Compiler warnings.Alan Mishchenko2013-10-171-4/+8
* Debugging and finetuning the flow.Alan Mishchenko2013-09-172-1/+3
* Unifying standard cell library representations.Alan Mishchenko2013-09-171-1/+1
* Adding switch 'ps -s' to skip counting buffers/inverters as nodes.Alan Mishchenko2013-09-021-2/+0
* Removing some old useless code.Alan Mishchenko2013-09-021-4/+0
* Removing some old useless code.Alan Mishchenko2013-09-022-257/+2
* Adding support for input slew and output capacitance to timer and gate-sizer ...Alan Mishchenko2013-07-241-2/+20
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-231-1/+1
* Improvements to post-mapping re-sizing.Alan Mishchenko2013-07-211-14/+16
* Memory leaks.Alan Mishchenko2013-07-211-1/+1
* Adding support for input slew (.input_drive) and output capacitance (.output_...Alan Mishchenko2013-07-212-0/+211
* Adding a wrapper around clock() for more accurate time counting in ABC.Alan Mishchenko2013-05-271-18/+18
* New MFS package.Alan Mishchenko2013-05-241-4/+4
* Commenting assertion that does not hold in AIGER 1.9, accoring to Baruch Sterin.Alan Mishchenko2013-05-131-1/+1
* Enabled 'cec' to be applied to networks derived from BLIF with EXDCs.Alan Mishchenko2013-04-181-3/+4
* Enabled reading the EXDC network by the default BLIF reader.Alan Mishchenko2013-04-182-5/+29
* Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ...Alan Mishchenko2013-04-181-2/+8
* Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ...Alan Mishchenko2013-04-171-4/+4
* Bug fix in 'write_pla'.Alan Mishchenko2013-04-151-1/+1
* Improvements to the hierarchy/timing manager.Alan Mishchenko2013-03-051-0/+2
* Fixing compilation problems on Linux-32 related to constants of type unsigned...Alan Mishchenko2013-01-301-12/+12
* Fixing C++ compilation issues.Alan Mishchenko2013-01-081-0/+3
* Improvements to LMS code.Alan Mishchenko2012-11-061-2/+2
* Adding binary file dumping for truth tables.Alan Mishchenko2012-10-251-1/+1
* Adding binary file dumping for truth tables.Alan Mishchenko2012-10-251-4/+18
* Added hierarchical BLIF output for mapping with LUT structures (write_blif -a...Alan Mishchenko2012-10-243-15/+296
* Bug fix in hierarchical BLIF reader.Alan Mishchenko2012-10-111-3/+2
* Added command to transform GIA into the file with truth tables for each output.Alan Mishchenko2012-10-101-0/+77
* Making explicit cast to 64-bit unsigned in a few places.Alan Mishchenko2012-10-091-1/+1
* C++ portability changes.Alan Mishchenko2012-10-031-1/+1
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