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* Commenting out bailout in 'print_cex' when CEX has latches initialized to 1.Alan Mishchenko2016-11-301-1/+2
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* New SAT-based optimization package.Alan Mishchenko2016-11-261-1/+1
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* Parser for JSON format.Alan Mishchenko2016-10-254-2/+391
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* Unsuccessful attempt to improve quality of factoring by limiting distance-1 ↵Alan Mishchenko2016-08-061-12/+67
| | | | merge during preprocessing.
* Extension in the detection code.Alan Mishchenko2016-07-191-0/+2
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* New multi-output PLA reader and preprocessor (read_plamo) (updated dist-1 ↵Alan Mishchenko2016-06-171-2/+54
| | | | merge).
* New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge).Alan Mishchenko2016-06-162-83/+355
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* Change to BENCH reader to read DFF with four inputs.Alan Mishchenko2016-06-161-7/+30
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* New multi-output PLA reader and preprocessor (read_plamo).Alan Mishchenko2016-06-163-0/+491
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* Detecting properties of internal nodes.Alan Mishchenko2016-06-121-0/+58
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* Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset).Alan Mishchenko2016-05-124-15/+30
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* Updating GIG parser.Alan Mishchenko2016-05-011-1/+1
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* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving ↵Alan Mishchenko2016-04-114-12/+17
| | | | AIG (cubes -x; st).
* An add-on to write Verilog for circuits mapped into simple gates.Alan Mishchenko2016-02-011-9/+22
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* Changing 'refactor' to work with truth tables.Alan Mishchenko2015-08-251-7/+0
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* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
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* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+7
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* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+10
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* Improvements to Cba data-structure.Alan Mishchenko2015-07-291-4/+4
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* Improvements to Cba data-structure.Alan Mishchenko2015-07-281-2/+2
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* Several additional fixed in the timing manager.Alan Mishchenko2015-04-072-2/+14
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* Improvements in reading timing information from BLIF.Alan Mishchenko2015-04-051-18/+127
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* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-041-20/+17
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* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-042-5/+6
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* Adding switch '-b' in 'read_pla'.Alan Mishchenko2015-03-184-16/+31
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* Propagating changes after updating flag of 'sop'.Alan Mishchenko2015-02-194-8/+8
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* Adding resource limit switch -C to 'sop'.Alan Mishchenko2015-02-114-9/+9
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* Fixed a typo in variable names.Alan Mishchenko2015-02-076-11/+11
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* Improvements and tuning of CBA with buffering/sizing.Alan Mishchenko2015-02-041-3/+12
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* Esperiments with MO PLA optimization.Alan Mishchenko2015-02-034-43/+303
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* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-3/+1
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* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-19/+93
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* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-22/+93
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* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-45/+61
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* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-0/+124
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* Integrating barrier buffers.Alan Mishchenko2014-12-131-2/+1
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* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-112-7/+10
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* Adding cyclicity check for netlist with boxes.Alan Mishchenko2014-11-102-3/+34
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* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-1/+1
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* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-281-1/+1
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* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
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* New word-level representation package.Alan Mishchenko2014-09-121-57/+0
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* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-0/+57
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* Compiler warning.Alan Mishchenko2014-08-271-2/+2
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* Improvements BLIF parser.Alan Mishchenko2014-08-271-0/+126
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* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-1/+1
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* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
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* Improvements to CNF generation.Alan Mishchenko2014-06-231-9/+35
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* Added quick GIG parser.Alan Mishchenko2014-06-191-0/+59
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* Bug fix in writing latch init values in 'write_aiger'.Alan Mishchenko2014-06-171-3/+3
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