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yosys-experimental
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Author
Age
Files
Lines
*
Bug fix in 'write_aiger_cex'.
Alan Mishchenko
2017-12-20
1
-0
/
+1
|
*
Adding switch -a to 'write_verilog' to write factored forms without XORs and ↵
Alan Mishchenko
2017-12-03
4
-16
/
+29
|
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MUXes.
*
Fixing minimize_assuptions using Glucose.
Alan Mishchenko
2017-10-02
1
-0
/
+1
|
*
Maintenance and updates.
Alan Mishchenko
2017-09-24
1
-1
/
+1
|
*
Compiler warnings.
Alan Mishchenko
2017-07-22
1
-2
/
+2
|
*
Adding PDR with abstraction.
Alan Mishchenko
2017-02-10
1
-1
/
+1
|
*
Improving CEX minimization.
Alan Mishchenko
2017-02-10
1
-1
/
+1
|
*
Improvements in AIG visualization.
Alan Mishchenko
2017-02-05
1
-2
/
+2
|
*
Updates to arithmetic verification.
Alan Mishchenko
2017-01-30
1
-1
/
+1
|
*
Commenting out bailout in 'print_cex' when CEX has latches initialized to 1.
Alan Mishchenko
2016-11-30
1
-1
/
+2
|
*
New SAT-based optimization package.
Alan Mishchenko
2016-11-26
1
-1
/
+1
|
*
Parser for JSON format.
Alan Mishchenko
2016-10-25
4
-2
/
+391
|
*
Unsuccessful attempt to improve quality of factoring by limiting distance-1 ↵
Alan Mishchenko
2016-08-06
1
-12
/
+67
|
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merge during preprocessing.
*
Extension in the detection code.
Alan Mishchenko
2016-07-19
1
-0
/
+2
|
*
New multi-output PLA reader and preprocessor (read_plamo) (updated dist-1 ↵
Alan Mishchenko
2016-06-17
1
-2
/
+54
|
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merge).
*
New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge).
Alan Mishchenko
2016-06-16
2
-83
/
+355
|
*
Change to BENCH reader to read DFF with four inputs.
Alan Mishchenko
2016-06-16
1
-7
/
+30
|
*
New multi-output PLA reader and preprocessor (read_plamo).
Alan Mishchenko
2016-06-16
3
-0
/
+491
|
*
Detecting properties of internal nodes.
Alan Mishchenko
2016-06-12
1
-0
/
+58
|
*
Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset).
Alan Mishchenko
2016-05-12
4
-15
/
+30
|
*
Updating GIG parser.
Alan Mishchenko
2016-05-01
1
-1
/
+1
|
*
Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving ↵
Alan Mishchenko
2016-04-11
4
-12
/
+17
|
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AIG (cubes -x; st).
*
An add-on to write Verilog for circuits mapped into simple gates.
Alan Mishchenko
2016-02-01
1
-9
/
+22
|
*
Changing 'refactor' to work with truth tables.
Alan Mishchenko
2015-08-25
1
-7
/
+0
|
*
Changes to be able to compile ABC without CUDD.
Alan Mishchenko
2015-08-24
1
-1
/
+1
|
*
Changes to be able to compile ABC without CUDD.
Alan Mishchenko
2015-08-24
1
-0
/
+7
|
*
Changes to be able to compile ABC without CUDD.
Alan Mishchenko
2015-08-24
1
-0
/
+10
|
*
Improvements to Cba data-structure.
Alan Mishchenko
2015-07-29
1
-4
/
+4
|
*
Improvements to Cba data-structure.
Alan Mishchenko
2015-07-28
1
-2
/
+2
|
*
Several additional fixed in the timing manager.
Alan Mishchenko
2015-04-07
2
-2
/
+14
|
*
Improvements in reading timing information from BLIF.
Alan Mishchenko
2015-04-05
1
-18
/
+127
|
*
Properly copying and saving the timing info in &get and &put.
Alan Mishchenko
2015-04-04
1
-20
/
+17
|
*
Properly copying and saving the timing info in &get and &put.
Alan Mishchenko
2015-04-04
2
-5
/
+6
|
*
Adding switch '-b' in 'read_pla'.
Alan Mishchenko
2015-03-18
4
-16
/
+31
|
*
Propagating changes after updating flag of 'sop'.
Alan Mishchenko
2015-02-19
4
-8
/
+8
|
*
Adding resource limit switch -C to 'sop'.
Alan Mishchenko
2015-02-11
4
-9
/
+9
|
*
Fixed a typo in variable names.
Alan Mishchenko
2015-02-07
6
-11
/
+11
|
*
Improvements and tuning of CBA with buffering/sizing.
Alan Mishchenko
2015-02-04
1
-3
/
+12
|
*
Esperiments with MO PLA optimization.
Alan Mishchenko
2015-02-03
4
-43
/
+303
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-3
/
+1
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-19
/
+93
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-22
/
+93
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-45
/
+61
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-0
/
+124
|
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-13
1
-2
/
+1
|
*
Generation of barrier-buffers for hierarchical design.
Alan Mishchenko
2014-11-11
2
-7
/
+10
|
*
Adding cyclicity check for netlist with boxes.
Alan Mishchenko
2014-11-10
2
-3
/
+34
|
*
Deriving AIG after cell mapping.
Alan Mishchenko
2014-10-03
1
-1
/
+1
|
*
Adding out-of-bounds checks to AIGER readers.
Alan Mishchenko
2014-09-28
1
-1
/
+1
|
*
Adding features to CNF generation.
Alan Mishchenko
2014-09-28
1
-6
/
+16
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