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* Procedure to compute truth tables for POs of GIA.Alan Mishchenko2012-07-071-2/+1
* Commands &fla_gla/&gla_fla to convert between flop-level and gate-level abstr...Alan Mishchenko2012-07-061-0/+106
* Tentatively retiring command &abs_start, &abs_cba, &abs_pba, &gla_cba, &gla_pba.Alan Mishchenko2012-07-061-10/+10
* Setting infinite default conflict limits in 'bmc', 'int', 'pdr'.Alan Mishchenko2012-07-061-4/+4
* Changing default conflict limits in bmc2 and bmc3 to be 0 (no limit).Alan Mishchenko2012-07-051-3/+3
* Other improvements to &vta and &gla.Alan Mishchenko2012-07-051-29/+91
* Other improvements to &vta and &gla.Alan Mishchenko2012-07-041-5/+13
* Reducing memory usage in bmc2 and bmc3.Alan Mishchenko2012-07-011-7/+19
* Bug fix in &vta.Alan Mishchenko2012-06-291-2/+2
* Gate level abstraction (command &gla).Alan Mishchenko2012-06-281-0/+1
* Gate level abstraction (command &gla).Alan Mishchenko2012-06-281-10/+187
* Added min-cut-based refinement of gate-level abstraction (command &gla_refine).Alan Mishchenko2012-06-241-0/+65
* Switch -A <file_name> to specify file name for dumping abstrated model with &...Alan Mishchenko2012-06-211-15/+27
* Changing 'if' to allow for delay optimization on sequential paths only.Alan Mishchenko2012-05-203-4/+7
* Better resolution of CO drivers. Should impact the QoR after 'if'.Alan Mishchenko2012-05-151-34/+0
* Added generation of multipliers in 'gen'.Alan Mishchenko2012-05-152-105/+160
* Changing the rules of assigning the names when AIG is converted into a logic ...Alan Mishchenko2012-05-111-4/+9
* Making sure cec -n and dsec -n do not remove the I/O names in the current net...Alan Mishchenko2012-05-081-0/+30
* Bug fix in fraig_restore.Alan Mishchenko2012-05-061-3/+6
* Compilation problem caused by multiple declarations.Alan Mishchenko2012-04-281-0/+1
* Added supporting dual-output seq miters in &trim.Alan Mishchenko2012-04-281-3/+8
* Added supporting dual-output seq miters in &iso.Alan Mishchenko2012-04-281-4/+8
* Set the failed output index if ORing of outputs was done in 'int'.Alan Mishchenko2012-04-271-1/+7
* Adding iterative refinement to 'addbuffs'.Alan Mishchenko2012-04-131-7/+13
* Updated used message for 'back_reach'.Alan Mishchenko2012-04-131-1/+1
* Adding iterative refinement to 'addbuffs'.Alan Mishchenko2012-04-111-4/+18
* Adding reverse order to 'addbuffs'.Alan Mishchenko2012-04-111-4/+10
* Improving printouts of critical path.Alan Mishchenko2012-04-091-1/+2
* Improving printouts of critical path.Alan Mishchenko2012-04-091-6/+3
* Improving printouts of critical path.Alan Mishchenko2012-04-092-5/+5
* Added dumping abstracted model in &vta.Alan Mishchenko2012-04-071-2/+6
* Improving printouts of critical path.Alan Mishchenko2012-04-061-3/+6
* Improving printouts of critical path.Alan Mishchenko2012-04-061-5/+5
* Improving printouts of critical path.Alan Mishchenko2012-04-062-20/+55
* Logic sharing for multi-input gates (silencing a warning).Alan Mishchenko2012-03-271-4/+0
* Enabling mapping into multi-input AND/OR gates.Alan Mishchenko2012-03-272-9/+94
* Logic sharing for multi-input gates (bug fix).Alan Mishchenko2012-03-261-1/+8
* Making demiter dump files in the current directory.Alan Mishchenko2012-03-261-5/+13
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-261-5/+10
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-251-4/+4
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-253-116/+305
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-251-1/+0
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-254-458/+604
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-253-0/+453
* Improving printouts of gates and support.Alan Mishchenko2012-03-242-10/+50
* Enabled demitering dual-output miters.Alan Mishchenko2012-03-233-47/+29
* Added command 'addbuffs' to create balanced CI/CO paths.Alan Mishchenko2012-03-231-0/+66
* Additional features for delay optimizationAlan Mishchenko2012-03-217-29/+378
* Switching to a variable-page-size memory manager for clauses and proofs.Alan Mishchenko2012-03-211-57/+0
* Alternative way of computing delay in SOP balancing.Alan Mishchenko2012-03-161-0/+2
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