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path: root/src/base/abci/abcDar.c
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* Added switches '-c' and '-n' to 'init'.Alan Mishchenko2014-11-021-1/+1
* Small changes.Alan Mishchenko2014-07-291-1/+1
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-281-0/+111
* Improvements to CNF generation.Alan Mishchenko2014-06-231-2/+2
* merge unfold2Jiang Long2014-06-041-1/+1
* Pass file name correctly.Alan Mishchenko2014-04-101-3/+4
* Mismatch in bmc3 printout.Alan Mishchenko2014-03-301-2/+2
* Updating code to support barrier buffers.Alan Mishchenko2014-03-181-0/+7
* Adding barrier buffers.Alan Mishchenko2014-03-161-0/+5
* Multi-output property solver.Alan Mishchenko2013-10-261-3/+4
* Multi-output property solver.Alan Mishchenko2013-10-231-38/+44
* Adding switch &get -m to import mapped network into the &-space.Alan Mishchenko2013-09-011-1/+1
* Adding timeout to command 'ind'.Alan Mishchenko2013-06-281-2/+2
* Unifying representation of mapping in GIA.Alan Mishchenko2013-06-251-1/+1
* Adding a wrapper around clock() for more accurate time counting in ABC.Alan Mishchenko2013-05-271-58/+58
* Adding runtime limit per output to multi-output DPR (pdr -H <num_sec>).Alan Mishchenko2013-05-031-15/+28
* Adding parameter structure for rarity simulation.Alan Mishchenko2013-04-171-2/+2
* Updating 'sim3' to move the design into the last rare state.Alan Mishchenko2013-04-011-2/+3
* Added dumping QDIMACS files in command 'qbf'.Alan Mishchenko2013-03-271-1/+1
* Adding new features to 'dualrail'.Alan Mishchenko2013-02-211-0/+3
* Adding new features to 'dualrail'.Alan Mishchenko2013-02-211-0/+23
* Added 'gap timeout' to bmc3 and sim3.Alan Mishchenko2013-02-151-2/+2
* Enabled detecting CEXes in multiple POs without stopping (sim3 -a).Alan Mishchenko2013-01-231-2/+5
* Enabled detecting CEXes in multiple POs without stopping (sim3 -a).Alan Mishchenko2013-01-231-2/+2
* Fixing C++ compilation issues.Alan Mishchenko2013-01-081-1/+1
* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-2/+2
* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-4/+4
* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-15/+29
* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-29/+18
* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-1/+9
* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-1/+5
* Isolating BMC code into a separate package.Alan Mishchenko2012-11-141-0/+1
* Performance bug fix in choice generation.Alan Mishchenko2012-11-091-11/+18
* Integrating GIA with LUT mapping.Alan Mishchenko2012-10-241-0/+144
* Extending BLIF parser/write to hangle multi-output cells.Alan Mishchenko2012-09-191-2/+2
* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-141-1/+1
* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-141-9/+12
* Unified print-out of property failures produced by all engines.Alan Mishchenko2012-09-091-5/+5
* Added new command &gla_shrink.Alan Mishchenko2012-09-041-2/+2
* Added simulation of comb circuits with user-specified patterns in command 'sim'.Alan Mishchenko2012-08-241-112/+16
* Fixing assertion mismatch in bmc2.Alan Mishchenko2012-07-141-1/+1
* Improvements in the proof-logging SAT solver.Alan Mishchenko2012-07-111-2/+2
* Adding several command-line arguments to 'dsat'.Alan Mishchenko2012-07-091-3/+3
* Updating memory print-out of &vta and &gla.Alan Mishchenko2012-07-081-1/+1
* Adding restart to rarity simulation in sim3 and &sim3.Alan Mishchenko2012-07-081-5/+5
* Updating project settings to have simpler include paths.Alan Mishchenko2012-07-071-19/+19
* Fixing time primtouts throughout the code.Alan Mishchenko2012-07-071-25/+34
* Changing the rules of assigning the names when AIG is converted into a logic ...Alan Mishchenko2012-05-111-4/+9
* Making demiter dump files in the current directory.Alan Mishchenko2012-03-261-5/+13
* Logic sharing for multi-input gates.Alan Mishchenko2012-03-251-0/+1
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