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iCE40/abc
yosys-experimental
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abci
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abcDar.c
Commit message (
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Author
Age
Files
Lines
*
Adding new features to 'dualrail'.
Alan Mishchenko
2013-02-21
1
-0
/
+3
*
Adding new features to 'dualrail'.
Alan Mishchenko
2013-02-21
1
-0
/
+23
*
Added 'gap timeout' to bmc3 and sim3.
Alan Mishchenko
2013-02-15
1
-2
/
+2
*
Enabled detecting CEXes in multiple POs without stopping (sim3 -a).
Alan Mishchenko
2013-01-23
1
-2
/
+5
*
Enabled detecting CEXes in multiple POs without stopping (sim3 -a).
Alan Mishchenko
2013-01-23
1
-2
/
+2
*
Fixing C++ compilation issues.
Alan Mishchenko
2013-01-08
1
-1
/
+1
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-2
/
+2
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-4
/
+4
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-15
/
+29
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-29
/
+18
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-1
/
+9
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-1
/
+5
*
Isolating BMC code into a separate package.
Alan Mishchenko
2012-11-14
1
-0
/
+1
*
Performance bug fix in choice generation.
Alan Mishchenko
2012-11-09
1
-11
/
+18
*
Integrating GIA with LUT mapping.
Alan Mishchenko
2012-10-24
1
-0
/
+144
*
Extending BLIF parser/write to hangle multi-output cells.
Alan Mishchenko
2012-09-19
1
-2
/
+2
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-1
/
+1
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-9
/
+12
*
Unified print-out of property failures produced by all engines.
Alan Mishchenko
2012-09-09
1
-5
/
+5
*
Added new command &gla_shrink.
Alan Mishchenko
2012-09-04
1
-2
/
+2
*
Added simulation of comb circuits with user-specified patterns in command 'sim'.
Alan Mishchenko
2012-08-24
1
-112
/
+16
*
Fixing assertion mismatch in bmc2.
Alan Mishchenko
2012-07-14
1
-1
/
+1
*
Improvements in the proof-logging SAT solver.
Alan Mishchenko
2012-07-11
1
-2
/
+2
*
Adding several command-line arguments to 'dsat'.
Alan Mishchenko
2012-07-09
1
-3
/
+3
*
Updating memory print-out of &vta and &gla.
Alan Mishchenko
2012-07-08
1
-1
/
+1
*
Adding restart to rarity simulation in sim3 and &sim3.
Alan Mishchenko
2012-07-08
1
-5
/
+5
*
Updating project settings to have simpler include paths.
Alan Mishchenko
2012-07-07
1
-19
/
+19
*
Fixing time primtouts throughout the code.
Alan Mishchenko
2012-07-07
1
-25
/
+34
*
Changing the rules of assigning the names when AIG is converted into a logic ...
Alan Mishchenko
2012-05-11
1
-4
/
+9
*
Making demiter dump files in the current directory.
Alan Mishchenko
2012-03-26
1
-5
/
+13
*
Logic sharing for multi-input gates.
Alan Mishchenko
2012-03-25
1
-0
/
+1
*
Enabled demitering dual-output miters.
Alan Mishchenko
2012-03-23
1
-1
/
+1
*
Additional features for delay optimization
Alan Mishchenko
2012-03-21
1
-0
/
+9
*
Renamed Aig_ObjPioNum to be Aig_ObjCioId.
Alan Mishchenko
2012-03-09
1
-2
/
+2
*
Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)...
Alan Mishchenko
2012-03-09
1
-14
/
+14
*
Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ...Ci...
Alan Mishchenko
2012-03-09
1
-16
/
+16
*
Redirecting printf messages.
Alan Mishchenko
2012-03-02
1
-181
/
+181
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default (bug f...
Alan Mishchenko
2012-02-25
1
-1
/
+1
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default.
Alan Mishchenko
2012-02-24
1
-8
/
+11
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default.
Alan Mishchenko
2012-02-24
1
-1
/
+8
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default.
Alan Mishchenko
2012-02-24
1
-51
/
+165
*
Silencing some of the gcc warnings.
Alan Mishchenko
2012-02-16
1
-3
/
+3
*
Added returning counter-example after BMC, which was recently added to 'dprove'.
Alan Mishchenko
2012-01-23
1
-0
/
+4
*
Major restructuring of the code.
Alan Mishchenko
2012-01-21
1
-23
/
+23
*
Replaced 'bmc' by 'bmc2' in 'dprove'. Added switches to 'dprove' to control B...
Alan Mishchenko
2012-01-19
1
-13
/
+15
*
Started experiments with a new solver.
Alan Mishchenko
2011-11-25
1
-3
/
+3
*
Fixed the overflow timeout problem in bmc/bmc2/bmc3/int/pdr/sim, etc.
Alan Mishchenko
2011-10-31
1
-5
/
+5
*
Changes to CNF generation code.
Alan Mishchenko
2011-10-17
1
-5
/
+18
*
Sequential cleanup with symbolic/ternary simulation.
Alan Mishchenko
2011-08-25
1
-1
/
+1
*
Sequential cleanup with symbolic/ternary simulation.
Alan Mishchenko
2011-08-24
1
-8
/
+8
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