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* Supporting LUT in NDR and WLC.Alan Mishchenko2019-04-051-0/+1
* Converting dch-style equivalences into scorr-style ones.Alan Mishchenko2019-04-051-0/+12
* Making 'ndr.h' fully independent of other ABC data-structures.Alan Mishchenko2019-03-231-12/+18
* Updating canonical form computation procedures (compiler warnings).Alan Mishchenko2019-03-051-1/+1
* Fixing several other type conversion warnings.Alan Mishchenko2019-03-051-24/+24
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-059-21/+21
* Fixing some warnings with -Wconversion.Alan Mishchenko2019-03-051-1/+1
* Suggested white-space changes for fewer gcc warnings.Alan Mishchenko2019-03-041-1/+1
* Adding switch -x to &ps to disable color printout.Alan Mishchenko2019-02-122-1/+18
* Compiler warning.Alan Mishchenko2019-01-301-1/+1
* Exploring other ways of CEX writing.Alan Mishchenko2019-01-215-6/+9
* Experiment with partitioned &scorr.Alan Mishchenko2019-01-151-0/+185
* Adding one API of GIA manager.Alan Mishchenko2019-01-121-0/+18
* Bug fix in deriving names for the miter output.Alan Mishchenko2019-01-101-4/+9
* Fixing float overflow during area-flow computation in &lf.Alan Mishchenko2018-12-131-0/+8
* Experiments with retiming (adding new APIs).Alan Mishchenko2018-12-091-0/+2
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-2110-17/+16
* Adding an option to write new-line after the comment symbol when dumping an A...Alan Mishchenko2018-11-201-2/+7
* Undoing some of the previous changes.Alan Mishchenko2018-11-151-1/+5
* Procedures to verify equivalence classes.Alan Mishchenko2018-11-111-1/+139
* Several recent bug fixes.Alan Mishchenko2018-11-042-4/+3
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-222-1/+27
* Experiments with word-level retiming.Alan Mishchenko2018-09-301-2/+5
* Preserving output names while deriving a miter.Alan Mishchenko2018-09-201-0/+26
* Preserving names while deriving a miter.Alan Mishchenko2018-09-201-0/+2
* Procedure to return seq equivalences.Alan Mishchenko2018-07-221-0/+68
* Extending NDR to support adder/subtractor.Alan Mishchenko2018-06-141-0/+36
* Bug fix (accessing unassigned memory).Alan Mishchenko2018-06-121-1/+7
* Compiler warnings.Alan Mishchenko2018-06-082-3/+4
* Supporting the decoder primitive in NDR and bit-blasting.Alan Mishchenko2018-06-052-1/+33
* Disabling unused feature in &nf.Alan Mishchenko2018-06-041-0/+2
* Supporting NMUX and SEL in NDR.Alan Mishchenko2018-05-241-0/+55
* Updates to NDR format (bug fixes).Alan Mishchenko2018-05-032-21/+29
* Updates to NDR format (flops, memories, signed mult, etc).Alan Mishchenko2018-04-292-61/+244
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-252-0/+186
* Adding adder-subtractor primitive.Alan Mishchenko2018-04-111-1/+3
* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-4/+8
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-2/+106
* Updating &mfs to support hard objects.Alan Mishchenko2018-03-231-2/+25
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-222-2/+4
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-241-0/+98
* Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+19
* Experiments with LUT mapping.Alan Mishchenko2018-02-102-9/+47
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+2
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