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* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-114-2/+9
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* Invalidate packing after mapping is updated.Alan Mishchenko2016-05-091-0/+1
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* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-082-12/+225
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* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-0710-1692/+444
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* Update to &show to show AIGs with XORs and MUXes (derived by &st -m).Alan Mishchenko2016-05-041-0/+1
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* Update to &show to show AIGs with XORs and MUXes (derived by &st -m).Alan Mishchenko2016-05-041-2/+28
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* Updating GIG parser.Alan Mishchenko2016-05-011-180/+384
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* Fanout restriction in &edge.Alan Mishchenko2016-04-301-11/+33
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* Experiments with arithmetic circuits.Alan Mishchenko2016-04-282-0/+290
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* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-2710-18/+16
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* Extending &satlut to work for 6-LUTs.Alan Mishchenko2016-04-271-4/+11
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* Using seed assignment of edges in &edge.Alan Mishchenko2016-04-273-2/+17
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* Improved algo for edge computation.Alan Mishchenko2016-04-241-1/+1
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* Improved algo for edge computation.Alan Mishchenko2016-04-242-7/+90
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* Improved algo for edge computation.Alan Mishchenko2016-04-231-48/+58
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* Improved algo for edge computation.Alan Mishchenko2016-04-226-7/+430
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* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-134-1/+360
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* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving ↵Alan Mishchenko2016-04-111-10/+45
| | | | AIG (cubes -x; st).
* Supporting edge information during mapping.Alan Mishchenko2016-04-117-43/+57
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* Command &esop to convert AIG into ESOP.Alan Mishchenko2016-04-092-0/+507
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* Adding hashing of windows in &satlut.Alan Mishchenko2016-04-071-3/+19
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* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-074-6/+69
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* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-17/+44
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* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-074-20/+231
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* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-076-145/+501
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* Supporting edge information during mapping.Alan Mishchenko2016-04-065-0/+295
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-043-110/+207
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-150/+249
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-043-18/+97
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-032-79/+303
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* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-033-2/+376
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* Windowing for technology mapping.Alan Mishchenko2016-03-307-183/+450
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* Windowing for technology mapping.Alan Mishchenko2016-03-295-13/+432
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* Procedure to check inductive invariant for Gia package.Alan Mishchenko2016-03-211-0/+61
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* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-133-1/+572
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* Experiments with SAT-based mapping.Alan Mishchenko2016-02-082-94/+175
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* Experiments with SAT-based mapping.Alan Mishchenko2016-02-073-0/+631
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* New command to dump LUT network.Alan Mishchenko2016-01-163-0/+135
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* Experiments with SAT-based mapping.Alan Mishchenko2016-01-141-50/+83
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* Experiments with SAT-based mapping.Alan Mishchenko2016-01-101-0/+155
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* Consolidating timing manager Scl_Con_t and propagating changes.Alan Mishchenko2016-01-071-10/+8
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* Adding switch &miter -x for XORs outputs of two word-level POs.Alan Mishchenko2016-01-062-0/+32
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* Fixing last-minute bug fix in &nf.Alan Mishchenko2016-01-051-2/+2
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* Buf fix in floating time reporting.Alan Mishchenko2016-01-051-20/+21
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* Fix in &nf for the case when PO can be driven by an inverter.Alan Mishchenko2016-01-051-0/+5
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* Fix in &nf for the case when PO can be driven by an inverter.Alan Mishchenko2016-01-051-0/+30
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* Migrating to using 32-bit timing representation in &nf.Alan Mishchenko2016-01-051-151/+148
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* Migrating back to using 'float' in area-flow computation in &nf.Alan Mishchenko2016-01-052-69/+76
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* g++ compiler warnings.Alan Mishchenko2015-11-082-3/+2
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* Improvements to 'satclp' (unfinished).Alan Mishchenko2015-11-061-0/+2
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