| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Adding API to dump MiniAIG into a Verilog file and other small changes. | Alan Mishchenko | 2017-10-22 | 1 | -7/+72 |
| * | Compiler warnings. | Alan Mishchenko | 2017-04-28 | 1 | -6/+6 |
| * | Adding support for minimalistic representation of LUT mapping. | Alan Mishchenko | 2016-12-05 | 1 | -0/+1 |
| * | Fix C++ compilation errors | Baruch Sterin | 2015-10-16 | 1 | -0/+4 |
| * | Added procedure to check correctness of the topo order during AIG construction. | Alan Mishchenko | 2012-10-10 | 1 | -0/+27 |
| * | Added serialization of Mini AIG. | Alan Mishchenko | 2012-09-29 | 1 | -6/+62 |
| * | Experiments with mini AIG manager. | Alan Mishchenko | 2012-09-29 | 1 | -0/+193 |
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index : iCE40/abc | |
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