| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Adding API to dump MiniAIG into a Verilog file and other small changes. | Alan Mishchenko | 2017-10-22 | 1 | -0/+1 |
| * | Compiler warnings. | Alan Mishchenko | 2017-07-22 | 1 | -1/+1 |
| * | Bug fix in MiniLUT APIs. | Alan Mishchenko | 2017-07-12 | 1 | -1/+31 |
| * | Making MiniLUT work for more than 6 inputs. | Alan Mishchenko | 2017-07-08 | 1 | -17/+38 |
| * | Synchronizing various data-structures. | Alan Mishchenko | 2017-07-04 | 1 | -10/+124 |
| * | Corner-case bug in MiniLUT. | Alan Mishchenko | 2017-01-25 | 1 | -0/+1 |
| * | Dealing wit COs driven by inverters in MiniLUT. | Alan Mishchenko | 2017-01-06 | 1 | -2/+38 |
| * | Adding support for minimalistic representation of LUT mapping. | Alan Mishchenko | 2016-12-05 | 1 | -1/+1 |
| * | Adding support for minimalistic representation of LUT mapping. | Alan Mishchenko | 2016-12-05 | 1 | -0/+182 |
| * | Reading/writing MiniAIG and several minor changes. | Alan Mishchenko | 2013-05-03 | 1 | -0/+2 |
| * | Reading/writing MiniAIG and several minor changes. | Alan Mishchenko | 2013-05-03 | 1 | -0/+187 |
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index : iCE40/abc | |
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