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iCE40/abc
yosys-experimental
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src
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aig
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gia
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giaMini.c
Commit message (
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Author
Age
Files
Lines
*
New API for external calls.
Alan Mishchenko
2021-10-26
1
-0
/
+16
*
Improving MiniAIG and name manager.
Alan Mishchenko
2021-09-16
1
-11
/
+15
*
Further debugging of MiniLUT APIs.
Alan Mishchenko
2021-09-16
1
-1
/
+72
*
Bug fix in MiniLUT code.
Alan Mishchenko
2021-09-13
1
-1
/
+1
*
Additional MiniLUT API.
Alan Mishchenko
2021-09-03
1
-0
/
+17
*
New ways of reading MiniAIG.
Alan Mishchenko
2020-07-29
1
-1
/
+1
*
New ways of reading MiniAIG.
Alan Mishchenko
2020-07-29
1
-0
/
+268
*
Corner-case bug in MiniLUT computation.
Alan Mishchenko
2020-04-02
1
-0
/
+1
*
Adding switch &w -n to modify the comment section of the AIGER file written.
Alan Mishchenko
2018-11-21
1
-3
/
+3
*
Procedures to verify equivalence classes.
Alan Mishchenko
2018-11-11
1
-1
/
+139
*
Procedure to return seq equivalences.
Alan Mishchenko
2018-07-22
1
-0
/
+68
*
Making sure duplicated inverters are not created.
Alan Mishchenko
2018-04-11
1
-3
/
+9
*
Extending MiniLUT to return attributes.
Alan Mishchenko
2018-02-11
1
-0
/
+19
*
Adding API to dump MiniAIG into a Verilog file and other small changes.
Alan Mishchenko
2017-10-22
1
-0
/
+1
*
Compiler warnings.
Alan Mishchenko
2017-07-22
1
-1
/
+1
*
Bug fix in MiniLUT APIs.
Alan Mishchenko
2017-07-12
1
-1
/
+31
*
Making MiniLUT work for more than 6 inputs.
Alan Mishchenko
2017-07-08
1
-17
/
+38
*
Synchronizing various data-structures.
Alan Mishchenko
2017-07-04
1
-10
/
+124
*
Corner-case bug in MiniLUT.
Alan Mishchenko
2017-01-25
1
-0
/
+1
*
Dealing wit COs driven by inverters in MiniLUT.
Alan Mishchenko
2017-01-06
1
-2
/
+38
*
Adding support for minimalistic representation of LUT mapping.
Alan Mishchenko
2016-12-05
1
-1
/
+1
*
Adding support for minimalistic representation of LUT mapping.
Alan Mishchenko
2016-12-05
1
-0
/
+182
*
Reading/writing MiniAIG and several minor changes.
Alan Mishchenko
2013-05-03
1
-0
/
+2
*
Reading/writing MiniAIG and several minor changes.
Alan Mishchenko
2013-05-03
1
-0
/
+187