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path: root/src/aig/gia/giaMan.c
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* Experiments with word-level data structures.Alan Mishchenko2022-02-021-1/+1
* Various changes.Alan Mishchenko2021-10-221-0/+1
* Various changes.Alan Mishchenko2021-09-301-0/+1
* Adding command &reshape.Alan Mishchenko2021-09-211-2/+0
* Various changes.Alan Mishchenko2021-09-021-0/+3
* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-23/+66
* Updating LUT synthesis code.Alan Mishchenko2021-05-261-1/+1
* Improvements to the SAT sweeper.Alan Mishchenko2020-11-141-0/+1
* Experiments with simulation-based engines.Alan Mishchenko2020-03-221-0/+1
* Various changes.Alan Mishchenko2020-03-211-0/+2
* Various changes.Alan Mishchenko2020-03-181-2/+4
* Ongoing changes to the simulator.Alan Mishchenko2020-03-091-7/+2
* Updating and extending simulation data structures.Alan Mishchenko2020-03-051-0/+1
* Adding commands to generate data for experiments.Alan Mishchenko2020-02-231-0/+7
* Adding AIG stats logging (using JSON format).Alan Mishchenko2020-01-161-0/+14
* Adding AIG stats logging.Alan Mishchenko2020-01-161-0/+25
* Changes to several APIs.Alan Mishchenko2019-11-011-5/+8
* Compiler warnings.Alan Mishchenko2019-10-271-1/+3
* Experiments with simulation.Alan Mishchenko2019-10-271-6/+42
* Fixing recent change to 'print_stats'.Alan Mishchenko2019-05-111-2/+2
* Adding switch -x to &ps to disable color printout.Alan Mishchenko2019-02-121-1/+17
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-2/+2
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-0/+185
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-231-0/+2
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-261-0/+1
* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-131-1/+1
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-131-2/+4
* Improvements to quantification.Alan Mishchenko2017-11-131-0/+2
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+1
* Small fix. Garanteeing pPars is not NULL before checking pPars->fSlacksBruno Schmitt2017-10-241-1/+1
* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-0/+320
* Supporting CO attributes in GIA.Alan Mishchenko2017-07-121-0/+1
* Synchronizing various data-structures.Alan Mishchenko2017-07-041-0/+3
* Adding new command 'dump_equiv'.Alan Mishchenko2016-07-211-0/+2
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-111-0/+1
* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-131-0/+2
* Supporting edge information during mapping.Alan Mishchenko2016-04-111-1/+1
* Supporting edge information during mapping.Alan Mishchenko2016-04-061-0/+26
* Windowing for technology mapping.Alan Mishchenko2016-03-301-0/+1
* Windowing for technology mapping.Alan Mishchenko2016-03-291-1/+1
* Adding support for black boxes in extended AIG.Alan Mishchenko2015-10-041-0/+2
* Adding support for flop init-states in extended AIG.Alan Mishchenko2015-10-041-0/+1
* New constraint manager and memory reporting 'ps'.Alan Mishchenko2015-09-081-0/+7
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-0/+2
* Diabling pin-permutation in &nf mapper.Alan Mishchenko2015-02-081-0/+1
* Integrating barrier buffers.Alan Mishchenko2014-12-081-0/+2
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-251-1/+1
* Adding integrity check for boxes and flops.Alan Mishchenko2014-11-251-4/+17
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-251-1/+1
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