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* Experiments with pattern generation.Alan Mishchenko2021-10-101-0/+4
* Experiments with SAT solving.Alan Mishchenko2021-10-091-0/+4
* New command &stochsyn for stochastic synthesis.Alan Mishchenko2021-10-061-0/+4
* Various changes.Alan Mishchenko2021-09-301-0/+8
* Adding command &reshape.Alan Mishchenko2021-09-211-0/+8
* Removing unused command.Alan Mishchenko2021-09-211-8/+0
* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-1/+1
* Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-121-1/+1
* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+1
* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+1
* Adding place holder file for resub experiments.Alan Mishchenko2021-06-241-0/+4
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-191-0/+4
* Updating cost function in &save/&load.Alan Mishchenko2021-05-081-0/+4
* Experiments with simulation.Alan Mishchenko2020-12-301-0/+4
* Compiler warnings.Alan Mishchenko2020-12-211-0/+4
* Upgrading the SAT solvers.Alan Mishchenko2020-11-141-0/+8
* Duplicating Glucose package.Alan Mishchenko2020-11-121-0/+108
* Experiments with SAT sweeping.Alan Mishchenko2020-11-091-0/+4
* Adding new resub code.Alan Mishchenko2020-07-081-0/+4
* Extend ISOP to return the truth table.Alan Mishchenko2020-04-021-4/+0
* Adding commands to generate data for experiments.Alan Mishchenko2020-02-221-0/+4
* Adding commands to generate data for experiments.Alan Mishchenko2020-02-221-0/+4
* Adding commands to generate data for experiments.Alan Mishchenko2020-02-211-0/+4
* Experimental simulation based code.Alan Mishchenko2020-02-061-0/+4
* Adding experimental command.Alan Mishchenko2019-12-141-0/+4
* Experiments with simulation.Alan Mishchenko2019-10-271-0/+4
* Adding new command handler for experimental procedures.Alan Mishchenko2019-04-171-0/+4
* Experiments with memory abstraction.Alan Mishchenko2019-01-271-0/+4
* Experiments with memory abstraction.Alan Mishchenko2019-01-221-0/+4
* Procedures to generate constant-argument multipliers.Alan Mishchenko2019-01-151-0/+4
* Procedures to generate constant-argument multipliers.Alan Mishchenko2019-01-091-0/+8
* Extending extra library with additional ZDD-based procedures.Alan Mishchenko2018-10-121-0/+8
* Experiments with word-level retiming.Alan Mishchenko2018-09-301-0/+32
* Expriments with functions.Alan Mishchenko2018-09-161-0/+4
* Experiments with function enumeration.Alan Mishchenko2018-08-011-0/+4
* Procedure to return seq equivalences.Alan Mishchenko2018-07-221-0/+4
* Adding command 'majgen'.Alan Mishchenko2018-07-041-0/+4
* Experiments with path enumeration.Alan Mishchenko2018-06-061-0/+4
* Simple BDD package.Alan Mishchenko2018-05-231-0/+4
* Memory abstraction.Alan Mishchenko2018-04-151-0/+4
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-221-4/+0
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-0/+12
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-281-0/+4
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-0/+4
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-0/+4
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-261-0/+4
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+4
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-221-0/+4
* Integrating old SAT solver into majexact and twoexact.Alan Mishchenko2017-10-191-0/+4
* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-0/+4
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