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* New multi-output PLA reader and preprocessor (read_plamo).Alan Mishchenko2016-06-161-0/+4
* Experiments with edge-based mapping.Alan Mishchenko2016-06-151-0/+4
* Detecting properties of internal nodes.Alan Mishchenko2016-06-071-0/+4
* New feature for area minimization in standard cell mapping.Alan Mishchenko2016-05-191-0/+4
* Experiments with generating sat assignments.Alan Mishchenko2016-05-151-0/+4
* New command 'expand' to expand SOPs against the offset.Alan Mishchenko2016-05-121-0/+4
* Cosmetic changes after incorporating new code of 'fxch'.Alan Mishchenko2016-05-111-4/+24
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-8/+32
* Experiments with arithmetic circuits.Alan Mishchenko2016-04-281-0/+4
* Improved algo for edge computation.Alan Mishchenko2016-04-221-0/+4
* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG...Alan Mishchenko2016-04-111-0/+32
* Command &esop to convert AIG into ESOP.Alan Mishchenko2016-04-091-0/+4
* Supporting edge information during mapping.Alan Mishchenko2016-04-061-0/+4
* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-031-0/+4
* Windowing for technology mapping.Alan Mishchenko2016-03-291-0/+4
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-131-0/+4
* Experiments with SAT-based mapping.Alan Mishchenko2016-02-071-0/+4
* Small changes to sort for timing.Alan Mishchenko2016-01-241-0/+4
* Extending and improving timing manager.Alan Mishchenko2015-11-081-1/+5
* Changes to VC6.0 makefile to accommodate new package 'opt/fret' and compiler ...Alan Mishchenko2015-10-281-0/+24
* Moving BDD-based threshold function detection to the BDD part of the code.Alan Mishchenko2015-10-161-4/+4
* Experiments with precomputation and matching.Alan Mishchenko2015-10-151-0/+4
* Experiments with functional matching.Alan Mishchenko2015-10-051-0/+4
* Experiments with functional matching.Alan Mishchenko2015-10-031-0/+4
* Naive LUT packing algorithm (command &pack).Alan Mishchenko2015-09-301-0/+4
* Experiments with LUT structure mapping.Alan Mishchenko2015-09-271-0/+4
* Adding new command &rex2gia.Alan Mishchenko2015-09-221-0/+4
* New constraint manager and memory reporting 'ps'.Alan Mishchenko2015-09-081-0/+4
* Experiments with SAT-based collapsing.Alan Mishchenko2015-09-031-0/+4
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-158/+158
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-196/+188
* Renaming Cba into Bac.Alan Mishchenko2015-07-211-3/+3
* Renaming Cba into Bac.Alan Mishchenko2015-07-211-29/+81
* Sequential word-level simulator for Wlc_Ntk_t.Alan Mishchenko2015-06-041-0/+4
* Scalable SOP manipulation package.Alan Mishchenko2015-03-231-0/+8
* Scalable SOP manipulation package.Alan Mishchenko2015-03-181-0/+32
* Experiments with SAT-based cube enumeration.Alan Mishchenko2015-03-051-0/+4
* Experiments with cube hashing.Alan Mishchenko2015-02-201-0/+4
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-181-0/+4
* Several improvements to CBA data-structure.Alan Mishchenko2015-02-161-0/+4
* Diabling pin-permutation in &nf mapper.Alan Mishchenko2015-02-081-0/+4
* Added SMT parser for Wlc_Ntk_t.Alan Mishchenko2015-02-071-0/+4
* Adding binary dump to CBA.Alan Mishchenko2015-02-051-0/+12
* Major rehash of the CBA code.Alan Mishchenko2015-01-311-7/+15
* New parser and framework.Alan Mishchenko2014-11-291-0/+52
* Improvements to word-level network package.Alan Mishchenko2014-11-141-0/+4
* Adding cyclicity check for netlist with boxes.Alan Mishchenko2014-11-101-0/+4
* Detecting full-adder chains and putting them into white boxes.Alan Mishchenko2014-11-091-0/+4
* Experimental implementation of BMC-related procedures.Alan Mishchenko2014-11-041-0/+4
* Changes to enable building external code.Alan Mishchenko2014-10-281-20/+0
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