summaryrefslogtreecommitdiffstats
path: root/abclib.dsp
Commit message (Expand)AuthorAgeFilesLines
* Updates to arithmetic verification.Alan Mishchenko2017-01-101-0/+4
* Updates to delay optimization project.Alan Mishchenko2017-01-021-0/+4
* Updates to delay optimization project.Alan Mishchenko2017-01-011-0/+4
* Updates to delay optimization project.Alan Mishchenko2016-12-271-0/+4
* Updates to delay optimization project.Alan Mishchenko2016-12-251-0/+4
* Several changes in arithmetic circuit manipulation.Alan Mishchenko2016-12-221-0/+4
* Bug fix in 'dsat <file.cnf>' when the number of classes in listed incorrectly.Alan Mishchenko2016-12-131-0/+48
* Adding support for minimalistic representation of LUT mapping.Alan Mishchenko2016-12-051-0/+4
* Changes to arithmetic logic detection.Alan Mishchenko2016-12-021-0/+12
* New command to profile arithmetic logic cones.Alan Mishchenko2016-11-261-0/+4
* New SAT-based optimization package.Alan Mishchenko2016-11-171-0/+32
* Fixed several compiler warnings.Alan Mishchenko2016-11-171-0/+12
* Isolating CBA types into a separate header.Alan Mishchenko2016-11-071-0/+4
* Parser for JSON format.Alan Mishchenko2016-10-251-0/+8
* Code for profiling arithmetic circuits.Alan Mishchenko2016-10-211-0/+4
* Experimental code for polynomial construction.Alan Mishchenko2016-09-051-0/+4
* Experimental code for polynomial construction.Alan Mishchenko2016-09-031-0/+8
* Updates to arithmetic verification.Alan Mishchenko2016-08-051-0/+4
* Adding new command 'dump_equiv'.Alan Mishchenko2016-07-211-0/+4
* Fix in reading initial state for edge-detection.Alan Mishchenko2016-07-191-0/+4
* New multi-output PLA reader and preprocessor (read_plamo).Alan Mishchenko2016-06-161-0/+4
* Experiments with edge-based mapping.Alan Mishchenko2016-06-151-0/+4
* Detecting properties of internal nodes.Alan Mishchenko2016-06-071-0/+4
* New feature for area minimization in standard cell mapping.Alan Mishchenko2016-05-191-0/+4
* Experiments with generating sat assignments.Alan Mishchenko2016-05-151-0/+4
* New command 'expand' to expand SOPs against the offset.Alan Mishchenko2016-05-121-0/+4
* Cosmetic changes after incorporating new code of 'fxch'.Alan Mishchenko2016-05-111-4/+24
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-8/+32
* Experiments with arithmetic circuits.Alan Mishchenko2016-04-281-0/+4
* Improved algo for edge computation.Alan Mishchenko2016-04-221-0/+4
* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG...Alan Mishchenko2016-04-111-0/+32
* Command &esop to convert AIG into ESOP.Alan Mishchenko2016-04-091-0/+4
* Supporting edge information during mapping.Alan Mishchenko2016-04-061-0/+4
* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-031-0/+4
* Windowing for technology mapping.Alan Mishchenko2016-03-291-0/+4
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-131-0/+4
* Experiments with SAT-based mapping.Alan Mishchenko2016-02-071-0/+4
* Small changes to sort for timing.Alan Mishchenko2016-01-241-0/+4
* Extending and improving timing manager.Alan Mishchenko2015-11-081-1/+5
* Changes to VC6.0 makefile to accommodate new package 'opt/fret' and compiler ...Alan Mishchenko2015-10-281-0/+24
* Moving BDD-based threshold function detection to the BDD part of the code.Alan Mishchenko2015-10-161-4/+4
* Experiments with precomputation and matching.Alan Mishchenko2015-10-151-0/+4
* Experiments with functional matching.Alan Mishchenko2015-10-051-0/+4
* Experiments with functional matching.Alan Mishchenko2015-10-031-0/+4
* Naive LUT packing algorithm (command &pack).Alan Mishchenko2015-09-301-0/+4
* Experiments with LUT structure mapping.Alan Mishchenko2015-09-271-0/+4
* Adding new command &rex2gia.Alan Mishchenko2015-09-221-0/+4
* New constraint manager and memory reporting 'ps'.Alan Mishchenko2015-09-081-0/+4
* Experiments with SAT-based collapsing.Alan Mishchenko2015-09-031-0/+4
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-158/+158
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 18:51:05 +0000