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* Integrated buffering and sizing.Alan Mishchenko2013-08-094-30/+67
* Improvements to buffering and sizing.Alan Mishchenko2013-08-098-30/+108
* Improvements to buffering and sizing.Alan Mishchenko2013-08-097-85/+242
* Improvements to buffering and sizing.Alan Mishchenko2013-08-093-67/+26
* Improvements to buffering and sizing.Alan Mishchenko2013-08-097-124/+181
* Compiler warnings.Alan Mishchenko2013-08-081-1/+1
* Integrated buffering and sizing.Alan Mishchenko2013-08-0816-99/+697
* Improvements to buffering and sizing.Alan Mishchenko2013-08-072-172/+159
* Improvements to buffering and sizing.Alan Mishchenko2013-08-0610-36/+510
* Improvements to buffering and sizing.Alan Mishchenko2013-08-065-20/+290
* Bug fix in 'int'.Alan Mishchenko2013-08-051-2/+2
* Bug fix in 'int'.Alan Mishchenko2013-08-051-42/+35
* Adding new (un)buffering with phase information.Alan Mishchenko2013-08-051-5/+30
* Adding new (un)buffering with phase information.Alan Mishchenko2013-08-056-10/+142
* Adding code to estimate buffer trees.Alan Mishchenko2013-08-057-43/+249
* Change from input slew to input drive strength in the BLIF file.Alan Mishchenko2013-08-045-10/+81
* Adding switch 'buffer -p' to enable buffing of the primary inputs.Alan Mishchenko2013-08-023-9/+16
* Code for parsing the transcripts.Alan Mishchenko2013-08-021-0/+18
* SAT solver with dynamic CNF loading.Alan Mishchenko2013-08-011-0/+210
* SAT solver with dynamic CNF loading.Alan Mishchenko2013-08-016-4/+139
* Internal parameter tuning.Alan Mishchenko2013-07-311-1/+1
* Code for parsing the transcripts.Alan Mishchenko2013-07-301-0/+124
* Parametrizing standard-cell mapper to account for the fanout delay.Alan Mishchenko2013-07-307-16/+68
* Added commands 'maxsize' and 'unbuffer'.Alan Mishchenko2013-07-291-3/+8
* Added commands 'maxsize' and 'unbuffer'.Alan Mishchenko2013-07-294-8/+198
* Compiler warning.Alan Mishchenko2013-07-291-1/+1
* Compiler warning.Alan Mishchenko2013-07-291-1/+1
* Improved buffering.Alan Mishchenko2013-07-299-337/+334
* Improved gate-sizing.Alan Mishchenko2013-07-298-3/+604
* Adding support for input slew and output capacitance to timer and gate-sizer ...Alan Mishchenko2013-07-243-4/+46
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-2413-82/+165
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-232-4/+5
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-231-1/+1
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-239-191/+277
* Bug fix and warning print.Alan Mishchenko2013-07-223-4/+47
* Enabling pin sorting in &if.Alan Mishchenko2013-07-221-0/+3
* Generating GENLIB library from SCL.Alan Mishchenko2013-07-228-185/+470
* Restructuring gate-sizing code trying to separate timing analysis.Alan Mishchenko2013-07-2114-302/+588
* New technology mapper.Alan Mishchenko2013-07-216-20/+25
* Improvements to post-mapping re-sizing.Alan Mishchenko2013-07-218-145/+175
* Memory leaks.Alan Mishchenko2013-07-212-9/+5
* Adding support for input slew and output capacitance to timer and gate-sizer.Alan Mishchenko2013-07-216-6/+99
* Adding support for input slew (.input_drive) and output capacitance (.output_...Alan Mishchenko2013-07-217-115/+387
* Improvements to the SCL package.Alan Mishchenko2013-07-206-159/+52
* Added command 'dnsize' to complement command 'upsize'.Alan Mishchenko2013-07-209-31/+734
* Experiment with 'pdr'.Alan Mishchenko2013-07-196-34/+189
* Small data-structure improvements in 'pdr'.Alan Mishchenko2013-07-193-25/+33
* Small changes to the printout in timing analysis.Alan Mishchenko2013-07-193-3/+5
* Temprary changes.Alan Mishchenko2013-07-181-1/+50
* New technology mapper.Alan Mishchenko2013-07-181-1/+1