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* Improving bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-132-16/+46
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-135-1/+655
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-125-2/+97
* Experiments with SAT-based mapping.Alan Mishchenko2016-02-083-95/+176
* Experiments with SAT-based mapping.Alan Mishchenko2016-02-075-0/+658
* Bug fix in liberty parser and change suggested by Clifford.Alan Mishchenko2016-02-072-1/+17
* Added recursive bit-blasting of a carry-lookahead adder.Alan Mishchenko2016-02-061-0/+51
* GENLIB parsing bug, which led to a crash.Alan Mishchenko2016-02-061-1/+4
* Fixing the problem of identically named signals in 'retime'.Alan Mishchenko2016-02-052-4/+4
* Making flop names after 'retime' more meaningful.Alan Mishchenko2016-02-032-4/+6
* Preserving internal signal names when 'strash' is not used.Alan Mishchenko2016-02-032-0/+7
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-1/+1
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-6/+13
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-024-11/+26
* An add-on to write Verilog for circuits mapped into simple gates.Alan Mishchenko2016-02-011-9/+22
* Rare bug fix in 'dch' resulting in choice nodes having internal fanout.Alan Mishchenko2016-01-311-1/+8
* Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...Alan Mishchenko2016-01-301-1/+1
* Small changes to sort for timing.Alan Mishchenko2016-01-242-3/+11
* Bug fix in 'aig', for the case of non-min-base SOPs.Alan Mishchenko2016-01-201-0/+1
* Generating sorting network as a PLA file.Alan Mishchenko2016-01-202-3/+52
* New command to dump LUT network.Alan Mishchenko2016-01-164-33/+232
* Changing the resource file to get rid of a warning on Linux.Alan Mishchenko2016-01-141-1/+1
* Compiler warning.Alan Mishchenko2016-01-141-1/+0
* Changes to PDR to compute f-inf clauses and import invariant (or clauses) as ...Alan Mishchenko2016-01-1415-68/+457
* Experiments with SAT-based mapping.Alan Mishchenko2016-01-141-50/+83
* Adding a way to derive cardinality constraint as a sorting network.Alan Mishchenko2016-01-131-4/+89
* Adding support for delay/area tradeoff.Alan Mishchenko2016-01-135-36/+70
* Integrating new CNF generation into &bmc.Alan Mishchenko2016-01-123-16/+26
* Better print-out of SOPs. Changing default of 'fx'. Updating 'satclp' to fine...Alan Mishchenko2016-01-125-10/+184
* Experiments with SAT-based mapping.Alan Mishchenko2016-01-101-0/+1
* Experiments with SAT-based mapping.Alan Mishchenko2016-01-102-0/+164
* Adding support of candinality clause to the SAT solver.Alan Mishchenko2016-01-105-7/+52
* Consolidating timing manager Scl_Con_t and propagating changes.Alan Mishchenko2016-01-0711-54/+93
* Bug fix in constraint file reader.Alan Mishchenko2016-01-072-2/+8
* Adding switch &miter -x for XORs outputs of two word-level POs.Alan Mishchenko2016-01-063-2/+57
* Fixing last-minute bug fix in &nf.Alan Mishchenko2016-01-051-2/+2
* Buf fix in floating time reporting.Alan Mishchenko2016-01-051-20/+21
* Fix in &nf for the case when PO can be driven by an inverter.Alan Mishchenko2016-01-051-0/+5
* Fix in &nf for the case when PO can be driven by an inverter.Alan Mishchenko2016-01-051-0/+30
* Migrating to using 32-bit timing representation in &nf.Alan Mishchenko2016-01-055-242/+239
* Migrating back to using 'float' in area-flow computation in &nf.Alan Mishchenko2016-01-055-77/+86
* Corner-case bug in 'read_profile'.Alan Mishchenko2015-12-221-1/+1
* Adding names to GIA inputs/outputs (addressing x-valued flops).Alan Mishchenko2015-12-221-1/+51
* Adding names to GIA inputs/outputs. Changing polarity of invariant generated...Alan Mishchenko2015-12-221-1/+1
* Adding names to GIA inputs/outputs. Changing polarity of invariant generated...Alan Mishchenko2015-12-211-0/+34
* Adding names to GIA inputs/outputs. Changing polarity of invariant generated...Alan Mishchenko2015-12-211-1/+1
* Corner-case bug in invariant profiling.Alan Mishchenko2015-12-181-0/+5
* Compiler warning.Alan Mishchenko2015-12-161-7/+0
* Branch merge.Alan Mishchenko2015-12-140-0/+0
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| * Extending Verilog parser to handle 'default' in the case-statement (bug fix).Alan Mishchenko2015-12-071-1/+4
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