iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-09	3	-67/+26
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-09	7	-124/+181
*	Compiler warnings.	Alan Mishchenko	2013-08-08	1	-1/+1
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-08	16	-99/+697
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-07	2	-172/+159
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-06	10	-36/+510
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-06	5	-20/+290
*	Bug fix in 'int'.	Alan Mishchenko	2013-08-05	1	-2/+2
*	Bug fix in 'int'.	Alan Mishchenko	2013-08-05	1	-42/+35
*	Adding new (un)buffering with phase information.	Alan Mishchenko	2013-08-05	1	-5/+30
*	Adding new (un)buffering with phase information.	Alan Mishchenko	2013-08-05	6	-10/+142
*	Adding code to estimate buffer trees.	Alan Mishchenko	2013-08-05	7	-43/+249
*	Change from input slew to input drive strength in the BLIF file.	Alan Mishchenko	2013-08-04	5	-10/+81
*	Adding switch 'buffer -p' to enable buffing of the primary inputs.	Alan Mishchenko	2013-08-02	3	-9/+16
*	Code for parsing the transcripts.	Alan Mishchenko	2013-08-02	1	-0/+18
*	SAT solver with dynamic CNF loading.	Alan Mishchenko	2013-08-01	1	-0/+210
*	SAT solver with dynamic CNF loading.	Alan Mishchenko	2013-08-01	6	-4/+139
*	Internal parameter tuning.	Alan Mishchenko	2013-07-31	1	-1/+1
*	Code for parsing the transcripts.	Alan Mishchenko	2013-07-30	1	-0/+124
*	Parametrizing standard-cell mapper to account for the fanout delay.	Alan Mishchenko	2013-07-30	7	-16/+68
*	Added commands 'maxsize' and 'unbuffer'.	Alan Mishchenko	2013-07-29	1	-3/+8
*	Added commands 'maxsize' and 'unbuffer'.	Alan Mishchenko	2013-07-29	4	-8/+198
*	Compiler warning.	Alan Mishchenko	2013-07-29	1	-1/+1
*	Compiler warning.	Alan Mishchenko	2013-07-29	1	-1/+1
*	Improved buffering.	Alan Mishchenko	2013-07-29	9	-337/+334
*	Improved gate-sizing.	Alan Mishchenko	2013-07-29	8	-3/+604
*	Adding support for input slew and output capacitance to timer and gate-sizer ...	Alan Mishchenko	2013-07-24	3	-4/+46
*	Tuning standard-cell mapping flow.	Alan Mishchenko	2013-07-24	13	-82/+165
*	Tuning standard-cell mapping flow.	Alan Mishchenko	2013-07-23	2	-4/+5
*	Tuning standard-cell mapping flow.	Alan Mishchenko	2013-07-23	1	-1/+1
*	Tuning standard-cell mapping flow.	Alan Mishchenko	2013-07-23	9	-191/+277
*	Bug fix and warning print.	Alan Mishchenko	2013-07-22	3	-4/+47
*	Enabling pin sorting in &if.	Alan Mishchenko	2013-07-22	1	-0/+3
*	Generating GENLIB library from SCL.	Alan Mishchenko	2013-07-22	8	-185/+470
*	Restructuring gate-sizing code trying to separate timing analysis.	Alan Mishchenko	2013-07-21	14	-302/+588
*	New technology mapper.	Alan Mishchenko	2013-07-21	6	-20/+25
*	Improvements to post-mapping re-sizing.	Alan Mishchenko	2013-07-21	8	-145/+175
*	Memory leaks.	Alan Mishchenko	2013-07-21	2	-9/+5
*	Adding support for input slew and output capacitance to timer and gate-sizer.	Alan Mishchenko	2013-07-21	6	-6/+99
*	Adding support for input slew (.input_drive) and output capacitance (.output_...	Alan Mishchenko	2013-07-21	7	-115/+387
*	Improvements to the SCL package.	Alan Mishchenko	2013-07-20	6	-159/+52
*	Added command 'dnsize' to complement command 'upsize'.	Alan Mishchenko	2013-07-20	9	-31/+734
*	Experiment with 'pdr'.	Alan Mishchenko	2013-07-19	6	-34/+189
*	Small data-structure improvements in 'pdr'.	Alan Mishchenko	2013-07-19	3	-25/+33
*	Small changes to the printout in timing analysis.	Alan Mishchenko	2013-07-19	3	-3/+5
*	Temprary changes.	Alan Mishchenko	2013-07-18	1	-1/+50
*	New technology mapper.	Alan Mishchenko	2013-07-18	1	-1/+1
*	New technology mapper.	Alan Mishchenko	2013-07-18	3	-53/+32
*	Temprary changes.	Alan Mishchenko	2013-07-18	1	-0/+49
*	New technology mapper.	Alan Mishchenko	2013-07-18	5	-86/+49