index
:
iCE40/abc
yosys-experimental
[no description]
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
*
Supporting edges in delay-optimization in &satlut.
Alan Mishchenko
2016-04-07
7
-151
/
+568
*
Supporting edge information during mapping.
Alan Mishchenko
2016-04-06
7
-2
/
+304
*
Supporting negative and reverse ranges of word-level variables in Wlc.
Alan Mishchenko
2016-04-04
6
-106
/
+168
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
4
-112
/
+214
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
3
-158
/
+269
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
4
-23
/
+112
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-03
3
-87
/
+330
*
Enabling native Gia visualization in &show.
Alan Mishchenko
2016-04-03
5
-7
/
+390
*
Allowing Cba manager to be derived from another Cba manager.
Alan Mishchenko
2016-04-02
2
-3
/
+3
*
Windowing for technology mapping.
Alan Mishchenko
2016-03-30
9
-190
/
+460
*
Windowing for technology mapping.
Alan Mishchenko
2016-03-29
6
-13
/
+436
*
Bug fix in truth table reading for funcs with less than 6 vars.
Alan Mishchenko
2016-03-28
3
-3
/
+3
*
Corner-case bug fix in 'satclp' with conflict limit.
Alan Mishchenko
2016-03-25
1
-5
/
+10
*
Sorting multiplier inputs based on the number of constant bits.
Alan Mishchenko
2016-03-24
1
-0
/
+21
*
Procedure to check inductive invariant for Gia package.
Alan Mishchenko
2016-03-21
1
-0
/
+61
*
Typo in operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
1
-1
/
+1
*
Supporting bit-wise XNOR operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
5
-3
/
+9
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-11
1
-6
/
+7
*
Adding API to convert Genlib into a simple Liberty.
Alan Mishchenko
2016-03-11
4
-1
/
+145
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-10
5
-11
/
+40
*
Change error to warning in 'scorr'.
Alan Mishchenko
2016-03-09
1
-2
/
+2
*
Bug fix in &fftest: not outputting test patterns when user test patterns are ...
Alan Mishchenko
2016-03-09
1
-8
/
+15
*
Supporting ~^ as equality operator in Wlc.
Alan Mishchenko
2016-03-04
1
-2
/
+3
*
New hierarchical TT NPN matching.
Alan Mishchenko
2016-02-26
4
-3
/
+170
*
Disabling formula cleaner to avoid problems with reading GENLIB on some libra...
Alan Mishchenko
2016-02-21
1
-1
/
+2
*
Re-doing the same change.
Alan Mishchenko
2016-02-15
1
-2
/
+2
*
Temporarily undoing one of the recent changes.
Alan Mishchenko
2016-02-15
1
-2
/
+2
*
Improving bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
2
-16
/
+46
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
5
-1
/
+655
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-12
5
-2
/
+97
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-02-08
3
-95
/
+176
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-02-07
5
-0
/
+658
*
Bug fix in liberty parser and change suggested by Clifford.
Alan Mishchenko
2016-02-07
2
-1
/
+17
*
Added recursive bit-blasting of a carry-lookahead adder.
Alan Mishchenko
2016-02-06
1
-0
/
+51
*
GENLIB parsing bug, which led to a crash.
Alan Mishchenko
2016-02-06
1
-1
/
+4
*
Fixing the problem of identically named signals in 'retime'.
Alan Mishchenko
2016-02-05
2
-4
/
+4
*
Making flop names after 'retime' more meaningful.
Alan Mishchenko
2016-02-03
2
-4
/
+6
*
Preserving internal signal names when 'strash' is not used.
Alan Mishchenko
2016-02-03
2
-0
/
+7
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-1
/
+1
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-6
/
+13
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
4
-11
/
+26
*
An add-on to write Verilog for circuits mapped into simple gates.
Alan Mishchenko
2016-02-01
1
-9
/
+22
*
Rare bug fix in 'dch' resulting in choice nodes having internal fanout.
Alan Mishchenko
2016-01-31
1
-1
/
+8
*
Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...
Alan Mishchenko
2016-01-30
1
-1
/
+1
*
Small changes to sort for timing.
Alan Mishchenko
2016-01-24
2
-3
/
+11
*
Bug fix in 'aig', for the case of non-min-base SOPs.
Alan Mishchenko
2016-01-20
1
-0
/
+1
*
Generating sorting network as a PLA file.
Alan Mishchenko
2016-01-20
2
-3
/
+52
*
New command to dump LUT network.
Alan Mishchenko
2016-01-16
4
-33
/
+232
*
Changing the resource file to get rid of a warning on Linux.
Alan Mishchenko
2016-01-14
1
-1
/
+1
*
Compiler warning.
Alan Mishchenko
2016-01-14
1
-1
/
+0
[next]