| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Improvement to reconv-driven windowing. | Alan Mishchenko | 2020-09-21 | 1 | -2/+3 |
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| * | Performance bug in k-resub and faster windowing. | Alan Mishchenko | 2020-09-18 | 2 | -26/+236 |
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| * | Experiment with using MUXes in k-resub engine. | Alan Mishchenko | 2020-09-17 | 1 | -6/+102 |
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| * | Compiler warnings. | Alan Mishchenko | 2020-09-17 | 2 | -2/+2 |
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| * | Improving MFFC computation code. | Alan Mishchenko | 2020-09-17 | 8 | -173/+202 |
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| * | Bug fixed in the resub code. | Alan Mishchenko | 2020-09-16 | 1 | -12/+73 |
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| * | Compiler warnings. | Alan Mishchenko | 2020-09-13 | 2 | -2/+2 |
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| * | Experiments with iterative synthesis. | Alan Mishchenko | 2020-09-13 | 7 | -42/+264 |
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| * | Deleting unused info left by the SAT sweeper. | Alan Mishchenko | 2020-09-10 | 1 | -0/+2 |
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| * | Adding switch &cec -w to print SAT solver stats. | Alan Mishchenko | 2020-09-06 | 4 | -3/+9 |
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| * | Fixing a typo in setting the miter type. | Alan Mishchenko | 2020-09-06 | 1 | -1/+1 |
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| * | Verifying new resub code. | Alan Mishchenko | 2020-09-06 | 2 | -19/+156 |
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| * | Experiments with ICCAD CAD benchmarks (Problem A). | Alan Mishchenko | 2020-09-03 | 2 | -7/+627 |
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| * | Experiments with window computation. | Alan Mishchenko | 2020-08-15 | 2 | -16/+365 |
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| * | Making &cec use precomputed simulation info. | Alan Mishchenko | 2020-08-12 | 4 | -12/+42 |
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| * | Extending &sim_read to use non-64-divisible pattern counts. | Alan Mishchenko | 2020-08-12 | 1 | -3/+13 |
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| * | New ways of reading MiniAIG. | Alan Mishchenko | 2020-07-29 | 1 | -1/+1 |
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| * | New ways of reading MiniAIG. | Alan Mishchenko | 2020-07-29 | 2 | -3/+278 |
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| * | Fixing new resub code. | Alan Mishchenko | 2020-07-20 | 1 | -2/+1 |
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| * | Fixing new resub code. | Alan Mishchenko | 2020-07-20 | 2 | -122/+215 |
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| * | Experiment with structural similarity. | Alan Mishchenko | 2020-07-16 | 6 | -0/+220 |
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| * | Correctly handling transfer of additional AIG info when AIG has no internal ↵ | Alan Mishchenko | 2020-07-13 | 2 | -4/+20 |
| | | | | | nodes. | ||||
| * | Fixing commands 'putontop' and 'topmost'; adding command 'bottommost'. | Alan Mishchenko | 2020-07-11 | 2 | -16/+171 |
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| * | Adding new resub code. | Alan Mishchenko | 2020-07-08 | 3 | -0/+584 |
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| * | Bug fix in &cec (properly updating the status after the corner case bug fix\). | Alan Mishchenko | 2020-06-24 | 1 | -0/+1 |
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| * | Bug fix in &cec (handling the case when the miter is disproved by the all-0 ↵ | Alan Mishchenko | 2020-06-24 | 1 | -5/+23 |
| | | | | | pattern). | ||||
| * | Compiler error. | Alan Mishchenko | 2020-06-04 | 1 | -4/+4 |
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| * | Experimental simulation. | Alan Mishchenko | 2020-06-04 | 2 | -10/+73 |
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| * | Experimental simulation. | Alan Mishchenko | 2020-06-03 | 2 | -1/+100 |
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| * | Dumping BDD variable order after 'clp'. | Alan Mishchenko | 2020-05-18 | 6 | -10/+27 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-15 | 7 | -263/+512 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-13 | 1 | -67/+221 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-11 | 1 | -4/+10 |
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| * | Adding new utility procedures. | Alan Mishchenko | 2020-05-11 | 6 | -45/+159 |
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| * | Adding new utility procedures. | Alan Mishchenko | 2020-05-10 | 3 | -9/+172 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-08 | 2 | -37/+125 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-07 | 1 | -35/+87 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-07 | 2 | -233/+450 |
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| * | Fixing the accidentally broken build. | Alan Mishchenko | 2020-05-06 | 1 | -1/+0 |
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| * | Experiment with permutations. | Alan Mishchenko | 2020-05-03 | 1 | -1/+1 |
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| * | Experiment with permutations. | Alan Mishchenko | 2020-05-03 | 2 | -1/+97 |
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| * | Compiler warnings and errors. | Alan Mishchenko | 2020-05-03 | 4 | -8/+8 |
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| * | Compiler warnings. | Alan Mishchenko | 2020-05-03 | 2 | -2/+0 |
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| * | Adding dumping of genlib library in Verilog. | Alan Mishchenko | 2020-05-03 | 2 | -30/+30 |
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| * | Adding dumping of genlib library in Verilog. | Alan Mishchenko | 2020-05-03 | 1 | -1/+1 |
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| * | Adding dumping of genlib library in Verilog. | Alan Mishchenko | 2020-05-03 | 4 | -7/+110 |
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| * | Experimental resubstitution. | Alan Mishchenko | 2020-05-03 | 9 | -5/+1049 |
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| * | Merge pull request #58 from whitequark/patch-2 | alanminko | 2020-04-30 | 1 | -2/+3 |
| |\ | | | | | Allow changing the `ar` binary | ||||
| | * | Allow changing the `ar` binary. | whitequark | 2020-04-30 | 1 | -2/+3 |
| | | | | | | | | | | | | | | | This is useful for cross-compilation, when build `ar` cannot handle the target object files. The invocation of `ranlib` is replaced with `ar s`, which is equivalent and simplifies the build system a bit. | ||||
| * | | Merge pull request #57 from whitequark/patch-1 | alanminko | 2020-04-30 | 1 | -2/+2 |
| |\ \ | | | | | | | Make use of setrlimit conditional on ABC_NO_RLIMIT | ||||
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index : iCE40/abc | |
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