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| * Fix violation of C strict aliasing rules.Jerry James2021-08-091-1/+3
* | Merge pull request #133 from twier/inv_get_name_mangling_fixalanminko2021-08-192-9/+43
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| * | Add comment to Wlc_NtkGetInv about vNamesIn's roleTobias Wiersema2021-08-191-0/+2
| * | Fix typo inifity -> infinity in inv_get helpTobias Wiersema2021-08-191-1/+1
| * | Add inv_get -f to read flop names from GIATobias Wiersema2021-08-192-8/+40
* | | Extending &trim to trim structurally equivalent primary outputs.Alan Mishchenko2021-08-193-3/+141
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* | Improving AIG to Verilog converter.Alan Mishchenko2021-08-174-28/+76
* | Suggested changes to collect and pass timing information (unused variable).Alan Mishchenko2021-08-121-1/+1
* | Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-122-8/+6
* | Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-122-13/+64
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* Making &cec support the miter circuit.Alan Mishchenko2021-08-051-0/+14
* Supporting simple operators in NDR.Alan Mishchenko2021-08-054-13/+53
* Adding node ordering options to command &dfs.Alan Mishchenko2021-08-053-29/+45
* Bug fix.Alan Mishchenko2021-08-031-1/+1
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-021-1/+0
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-024-12/+275
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-011-1/+1
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-014-32/+255
* Allow retiming to skip some logic.Alan Mishchenko2021-07-314-9/+69
* Upgrading choice computation.Alan Mishchenko2021-07-315-27/+38
* Experiments with cofactoring.Alan Mishchenko2021-07-312-6/+288
* Experimental simulation commands.Alan Mishchenko2021-07-256-67/+575
* Command to move CI/CO names.Alan Mishchenko2021-07-161-2/+3
* Command to move CI/CO names.Alan Mishchenko2021-07-163-7/+237
* Several unrelated changes.Alan Mishchenko2021-07-154-9/+186
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-07-135-4/+479
* Experiments with MUX decomposition.Alan Mishchenko2021-07-111-1/+1
* Experiments with CEC.Alan Mishchenko2021-07-104-9/+171
* Simple AIGER reader/writer.Alan Mishchenko2021-07-091-0/+141
* Experiments with MUX decomposition.Alan Mishchenko2021-07-082-2/+1
* Experiments with MUX decomposition.Alan Mishchenko2021-07-082-4/+5
* Experiments with MUX decomposition.Alan Mishchenko2021-07-083-2/+135
* Potential upgrade to 'dsec'.Alan Mishchenko2021-06-251-0/+24
* Adding place holder file for resub experiments.Alan Mishchenko2021-06-245-7/+67
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-198-67/+967
* Experiments with cut computation.Alan Mishchenko2021-06-082-2/+44
* Experiments with cut computation.Alan Mishchenko2021-06-052-4/+144
* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-021-2/+4
* Updating LUT synthesis code.Alan Mishchenko2021-05-264-7/+7
* Updating LUT synthesis code.Alan Mishchenko2021-05-253-66/+287
* Adding command &extract.Alan Mishchenko2021-05-182-1/+84
* Fixing memory leak in the SAT sweeper.Alan Mishchenko2021-05-161-1/+1
* Updating LUT synthesis code.Alan Mishchenko2021-05-161-1/+2
* Updating LUT synthesis code.Alan Mishchenko2021-05-168-127/+604
* Adding switch muxes -a to create networks of ADDs.Alan Mishchenko2021-05-154-15/+38
* Updating LUT synthesis code.Alan Mishchenko2021-05-112-38/+102
* Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-1111-21/+31
* Updating LUT synthesis code.Alan Mishchenko2021-05-115-46/+301
* Updating LUT synthesis code.Alan Mishchenko2021-05-084-2/+220
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