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-rw-r--r--src/map/scl/scl.c17
-rw-r--r--src/map/scl/sclBufSize.c66
-rw-r--r--src/map/scl/sclSize.c4
-rw-r--r--src/map/scl/sclSize.h10
4 files changed, 67 insertions, 30 deletions
diff --git a/src/map/scl/scl.c b/src/map/scl/scl.c
index bf1424fe..e899031c 100644
--- a/src/map/scl/scl.c
+++ b/src/map/scl/scl.c
@@ -707,14 +707,15 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
{
Abc_Ntk_t * pNtk = Abc_FrameReadNtk(pAbc);
Abc_Ntk_t * pNtkRes;
- int c, GainRatio, nDegree, fBufPis, fAddBufs, fVerbose;
- GainRatio = 200;
+ int c, GainRatio, nDegree, fSizeOnly, fBufPis, fAddBufs, fVerbose;
+ GainRatio = 150;
nDegree = 4;
+ fSizeOnly = 0;
fAddBufs = 0;
fBufPis = 0;
fVerbose = 0;
Extra_UtilGetoptReset();
- while ( ( c = Extra_UtilGetopt( argc, argv, "GNbpvh" ) ) != EOF )
+ while ( ( c = Extra_UtilGetopt( argc, argv, "GNsbpvh" ) ) != EOF )
{
switch ( c )
{
@@ -740,6 +741,9 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
if ( nDegree < 0 )
goto usage;
break;
+ case 's':
+ fSizeOnly ^= 1;
+ break;
case 'b':
fAddBufs ^= 1;
break;
@@ -766,13 +770,13 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -1, "This command can only be applied to a logic network.\n" );
return 1;
}
- if ( !fAddBufs && pNtk->vPhases == NULL )
+ if ( !fSizeOnly && !fAddBufs && pNtk->vPhases == NULL )
{
Abc_Print( -1, "Fanin phase information is not avaiable.\n" );
return 1;
}
// modify the current network
- pNtkRes = Abc_SclBufSizePerform( pNtk, (SC_Lib *)pAbc->pLibScl, GainRatio, nDegree, fAddBufs, fBufPis, fVerbose );
+ pNtkRes = Abc_SclBufSizePerform( pNtk, (SC_Lib *)pAbc->pLibScl, GainRatio, nDegree, fSizeOnly, fAddBufs, fBufPis, fVerbose );
if ( pNtkRes == NULL )
{
Abc_Print( -1, "The command has failed.\n" );
@@ -783,10 +787,11 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
- fprintf( pAbc->Err, "usage: bufsize [-GM num] [-bpvh]\n" );
+ fprintf( pAbc->Err, "usage: bufsize [-GM num] [-sbpvh]\n" );
fprintf( pAbc->Err, "\t performs buffering and sizing and mapped network\n" );
fprintf( pAbc->Err, "\t-G <num> : target gain percentage [default = %d]\n", GainRatio );
fprintf( pAbc->Err, "\t-M <num> : the maximum fanout degree [default = %d]\n", nDegree );
+ fprintf( pAbc->Err, "\t-s : toggle performing only sizing [default = %s]\n", fSizeOnly? "yes": "no" );
fprintf( pAbc->Err, "\t-b : toggle using buffers instead of inverters [default = %s]\n", fAddBufs? "yes": "no" );
fprintf( pAbc->Err, "\t-p : toggle buffering primary inputs [default = %s]\n", fBufPis? "yes": "no" );
fprintf( pAbc->Err, "\t-v : toggle printing verbose information [default = %s]\n", fVerbose? "yes": "no" );
diff --git a/src/map/scl/sclBufSize.c b/src/map/scl/sclBufSize.c
index fd4db57b..e4ba45cf 100644
--- a/src/map/scl/sclBufSize.c
+++ b/src/map/scl/sclBufSize.c
@@ -34,6 +34,7 @@ struct Bus_Man_t_
// parameters
float Gain; // target gain
int nDegree; // max branching factor
+ int fSizeOnly; // perform only sizing
int fAddBufs; // add buffers
int fBufPis; // use CI buffering
int fVerbose; // verbose
@@ -72,21 +73,22 @@ static inline void Bus_SclObjUpdateDept( Abc_Obj_t * p, float time ) { f
SeeAlso []
***********************************************************************/
-Bus_Man_t * Bus_ManStart( Abc_Ntk_t * pNtk, SC_Lib * pLib, int GainRatio, int nDegree, int fAddBufs, int fBufPis, int fVerbose )
+Bus_Man_t * Bus_ManStart( Abc_Ntk_t * pNtk, SC_Lib * pLib, int GainRatio, int nDegree, int fSizeOnly, int fAddBufs, int fBufPis, int fVerbose )
{
Bus_Man_t * p;
p = ABC_CALLOC( Bus_Man_t, 1 );
- p->Gain = 0.01 * GainRatio;
- p->nDegree = nDegree;
- p->fAddBufs = fAddBufs;
- p->fBufPis = fBufPis;
- p->fVerbose = fVerbose;
- p->pNtk = pNtk;
- p->pLib = pLib;
- p->pInv = Abc_SclFindInvertor(pLib, fAddBufs)->pAve;
- p->vCins = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
- p->vLoads = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
- p->vDepts = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
+ p->Gain = 0.01 * GainRatio;
+ p->nDegree = nDegree;
+ p->fSizeOnly = fSizeOnly;
+ p->fAddBufs = fAddBufs;
+ p->fBufPis = fBufPis;
+ p->fVerbose = fVerbose;
+ p->pNtk = pNtk;
+ p->pLib = pLib;
+ p->pInv = Abc_SclFindInvertor(pLib, fAddBufs)->pAve;
+ p->vCins = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
+ p->vLoads = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
+ p->vDepts = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
pNtk->pBSMan = p;
return p;
}
@@ -168,7 +170,11 @@ void Abc_NtkComputeFanoutCins( Abc_Obj_t * pObj )
int i;
Abc_ObjForEachFanout( pObj, pFanout, i )
if ( Abc_ObjIsNode(pFanout) )
- Bus_SclObjSetCin( pFanout, SC_CellPinCap( Abc_SclObjCell(pFanout), Abc_NodeFindFanin(pFanout, pObj) ) );
+ {
+ float cap = SC_CellPinCap( Abc_SclObjCell(pFanout), Abc_NodeFindFanin(pFanout, pObj) );
+ assert( cap > 0 );
+ Bus_SclObjSetCin( pFanout, cap );
+ }
}
float Abc_NtkComputeNodeLoad( Abc_Obj_t * pObj )
{
@@ -196,7 +202,7 @@ float Abc_NtkComputeNodeDept( Abc_Obj_t * pObj )
Edge = Scl_LibPinArrivalEstimate( Abc_SclObjCell(pFanout), Abc_NodeFindFanin(pFanout, pObj), Load );
Bus_SclObjUpdateDept( pObj, Dept + Edge );
assert( Edge > 0 );
- assert( Load > 0 );
+// assert( Load > 0 );
}
return Bus_SclObjDept( pObj );
}
@@ -318,11 +324,13 @@ void Abc_SclBufSize( Bus_Man_t * p )
SC_Cell * pCell, * pCellNew;
Vec_Ptr_t * vFanouts;
Abc_Obj_t * pObj, * pInv;
+ abctime clk = Abc_Clock();
+ float Dept, DeptMax = 0;
float Load, Cin;
int i;
vFanouts = Vec_PtrAlloc( 100 );
Abc_SclMioGates2SclGates( p->pLib, p->pNtk );
- Abc_NtkForEachNodeReverse( p->pNtk, pObj, i )
+ Abc_NtkForEachNodeReverse1( p->pNtk, pObj, i )
{
// compute load
Abc_NtkComputeFanoutCins( pObj );
@@ -331,7 +339,7 @@ void Abc_SclBufSize( Bus_Man_t * p )
pCell = Abc_SclObjCell( pObj );
Cin = SC_CellPinCapAve( pCell->pAve );
// consider upsizing the gate
- if ( Load > p->Gain * Cin )
+ if ( !p->fSizeOnly && Load > p->Gain * Cin )
{
// add one or more inverters
Abc_NodeCollectFanouts( pObj, vFanouts );
@@ -347,27 +355,43 @@ void Abc_SclBufSize( Bus_Man_t * p )
assert( Abc_ObjFanin0(pInv) == NULL );
Abc_ObjAddFanin( pInv, pObj );
Bus_SclObjSetLoad( pObj, Load );
- }
+ }
// create cell
pCellNew = Abc_SclFindSmallestGate( pCell, Load / p->Gain );
Abc_SclObjSetCell( pObj, pCellNew );
- Abc_NtkComputeNodeDept( pObj );
+ Dept = Abc_NtkComputeNodeDept( pObj );
+ DeptMax = Abc_MaxFloat( DeptMax, Dept );
+ if ( p->fVerbose )
+ {
+ printf( "Node %7d : ", i );
+ printf( "%12s ", pCellNew->pName );
+ printf( "(%2d/%2d) ", pCellNew->Order, pCellNew->nGates );
+ printf( "gain =%5.2f ", Load / SC_CellPinCapAve(pCellNew) );
+ printf( "dept =%7.0f ps ", SC_LibTimePs(p->pLib, Dept) );
+ printf( "\n" );
+ }
}
Abc_SclSclGates2MioGates( p->pLib, p->pNtk );
Vec_PtrFree( vFanouts );
+ if ( p->fVerbose )
+ {
+ printf( "Largest departure time = %7.0f ps ", SC_LibTimePs(p->pLib, DeptMax) );
+ Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
+ }
}
-Abc_Ntk_t * Abc_SclBufSizePerform( Abc_Ntk_t * pNtk, SC_Lib * pLib, int GainRatio, int nDegree, int fAddBufs, int fBufPis, int fVerbose )
+Abc_Ntk_t * Abc_SclBufSizePerform( Abc_Ntk_t * pNtk, SC_Lib * pLib, int GainRatio, int nDegree, int fSizeOnly, int fAddBufs, int fBufPis, int fVerbose )
{
Abc_Ntk_t * pNtkNew;
Bus_Man_t * p;
if ( !Abc_SclCheckNtk( pNtk, 0 ) )
return NULL;
Abc_SclReportDupFanins( pNtk );
- p = Bus_ManStart( pNtk, pLib, GainRatio, nDegree, fAddBufs, fBufPis, fVerbose );
+ p = Bus_ManStart( pNtk, pLib, GainRatio, nDegree, fSizeOnly, fAddBufs, fBufPis, fVerbose );
Bus_ManReadInOutLoads( p );
Abc_SclBufSize( p );
Bus_ManStop( p );
- Vec_IntFillExtra( pNtk->vPhases, Abc_NtkObjNumMax(pNtk), 0 );
+ if ( pNtk->vPhases )
+ Vec_IntFillExtra( pNtk->vPhases, Abc_NtkObjNumMax(pNtk), 0 );
pNtkNew = Abc_NtkDupDfs( pNtk );
return pNtkNew;
}
diff --git a/src/map/scl/sclSize.c b/src/map/scl/sclSize.c
index fcc32da9..122c8b56 100644
--- a/src/map/scl/sclSize.c
+++ b/src/map/scl/sclSize.c
@@ -109,7 +109,7 @@ Abc_Obj_t * Abc_SclFindMostCriticalFanin( SC_Man * p, int * pfRise, Abc_Obj_t *
static inline void Abc_SclTimeNodePrint( SC_Man * p, Abc_Obj_t * pObj, int fRise, int Length, float maxDelay )
{
SC_Cell * pCell = Abc_ObjIsNode(pObj) ? Abc_SclObjCell(pObj) : NULL;
- printf( "%6d : ", Abc_ObjId(pObj) );
+ printf( "%8d : ", Abc_ObjId(pObj) );
printf( "%d ", Abc_ObjFaninNum(pObj) );
printf( "%4d ", Abc_ObjFanoutNum(pObj) );
printf( "%-*s ", Length, pCell ? pCell->pName : "pi" );
@@ -170,7 +170,7 @@ void Abc_SclTimeNtkPrint( SC_Man * p, int fShowAll, int fPrintPath )
pObj = Abc_ObjFanin0(pPivot);
while ( pObj )//&& Abc_ObjIsNode(pObj) )
{
- printf( "Path%3d -- ", i-- );
+ printf( "Path%3d --", i-- );
Abc_SclTimeNodePrint( p, pObj, fRise, nLength, maxDelay );
pObj = Abc_SclFindMostCriticalFanin( p, &fRise, pObj );
}
diff --git a/src/map/scl/sclSize.h b/src/map/scl/sclSize.h
index eeade9bc..2c7a0640 100644
--- a/src/map/scl/sclSize.h
+++ b/src/map/scl/sclSize.h
@@ -188,6 +188,14 @@ static inline SC_Man * Abc_SclManAlloc( SC_Lib * pLib, Abc_Ntk_t * pNtk )
}
static inline void Abc_SclManFree( SC_Man * p )
{
+ Abc_Obj_t * pObj;
+ int i;
+ // set CI/CO ids
+ Abc_NtkForEachCi( p->pNtk, pObj, i )
+ pObj->iData = 0;
+ Abc_NtkForEachCo( p->pNtk, pObj, i )
+ pObj->iData = 0;
+ // other
p->pNtk->pSCLib = NULL;
Vec_IntFreeP( &p->pNtk->vGates );
Vec_IntFreeP( &p->vNodeIter );
@@ -485,7 +493,7 @@ static inline void Abc_SclDumpStats( SC_Man * p, char * pFileName, abctime Time
}
/*=== sclBufSize.c ===============================================================*/
-extern Abc_Ntk_t * Abc_SclBufSizePerform( Abc_Ntk_t * pNtk, SC_Lib * pLib, int GainRatio, int nDegree, int fAddBufs, int fBufPis, int fVerbose );
+extern Abc_Ntk_t * Abc_SclBufSizePerform( Abc_Ntk_t * pNtk, SC_Lib * pLib, int GainRatio, int nDegree, int fSizeOnly, int fAddBufs, int fBufPis, int fVerbose );
/*=== sclBuffer.c ===============================================================*/
extern int Abc_SclIsInv( Abc_Obj_t * pObj );
extern void Abc_NodeInvUpdateFanPolarity( Abc_Obj_t * pObj );
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 15:24:09 +0000