6 files changed, 50 insertions, 10 deletions

diff --git a/src/map/fpga/fpga.h b/src/map/fpga/fpga.h
index ee65f7a8..df4a9189 100644
--- a/src/map/fpga/fpga.h
+++ b/src/map/fpga/fpga.h
@@ -96,8 +96,9 @@ extern void            Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNode
 extern void            Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices );
 extern void            Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose );
 extern void            Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching );
-extern void            Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget );
+extern void            Fpga_ManSetLatchPaths( Fpga_Man_t * p, int fLatchPaths );
 extern void            Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches );
+extern void            Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget );
 extern void            Fpga_ManSetName( Fpga_Man_t * p, char * pFileName );
 
 extern int             Fpga_LibReadLutMax( Fpga_LutLib_t * pLib );
diff --git a/src/map/fpga/fpgaCore.c b/src/map/fpga/fpgaCore.c
index 36842ecf..fbf33816 100644
--- a/src/map/fpga/fpgaCore.c
+++ b/src/map/fpga/fpgaCore.c
@@ -100,6 +100,9 @@ int Fpga_MappingPostProcess( Fpga_Man_t * p )
     float aAreaTotalCur, aAreaTotalCur2;
     int Iter, clk;
 
+if ( p->fVerbose )
+    printf( "Best clock period = %5.2f\n", Fpga_TimeComputeArrivalMax(p) );
+
     // compute area, set references, and collect nodes used in the mapping
     Iter = 1;
     aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
diff --git a/src/map/fpga/fpgaCreate.c b/src/map/fpga/fpgaCreate.c
index e6a9716f..41bea4d0 100644
--- a/src/map/fpga/fpgaCreate.c
+++ b/src/map/fpga/fpgaCreate.c
@@ -66,8 +66,9 @@ void            Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNodes ) { p
 void            Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices )         { p->nChoices = nChoices;          }   
 void            Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose )           { p->fVerbose = fVerbose;          }   
 void            Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching )       { p->fSwitching = fSwitching;      }   
-void            Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget )  { p->DelayTarget = DelayTarget;    }   
+void            Fpga_ManSetLatchPaths( Fpga_Man_t * p, int fLatchPaths )     { p->fLatchPaths = fLatchPaths;    }   
 void            Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches )          { p->nLatches = nLatches;          }   
+void            Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget )  { p->DelayTarget = DelayTarget;    }   
 void            Fpga_ManSetName( Fpga_Man_t * p, char * pFileName )          { p->pFileName = pFileName;        }   
 
 /**Function*************************************************************
diff --git a/src/map/fpga/fpgaCut.c b/src/map/fpga/fpgaCut.c
index dc2e420b..01562708 100644
--- a/src/map/fpga/fpgaCut.c
+++ b/src/map/fpga/fpgaCut.c
@@ -35,9 +35,9 @@ struct Fpga_CutTableStrutct_t
 };
 
 // the largest number of cuts considered
-#define  FPGA_CUTS_MAX_COMPUTE   5000
+#define  FPGA_CUTS_MAX_COMPUTE   500
 // the largest number of cuts used
-#define  FPGA_CUTS_MAX_USE       2000
+#define  FPGA_CUTS_MAX_USE       200
 
 // primes used to compute the hash key
 static int s_HashPrimes[10] = { 109, 499, 557, 619, 631, 709, 797, 881, 907, 991 };
diff --git a/src/map/fpga/fpgaInt.h b/src/map/fpga/fpgaInt.h
index 318def25..74ab321c 100644
--- a/src/map/fpga/fpgaInt.h
+++ b/src/map/fpga/fpgaInt.h
@@ -122,6 +122,7 @@ struct Fpga_ManStruct_t_
     int                 fAreaRecovery; // the flag to use area flow as the first parameter
     int                 fVerbose;      // the verbosiness flag
     int                 fSwitching;    // minimize the switching activity (instead of area)
+    int                 fLatchPaths;   // optimize latch paths for delay, other paths for area
     int                 nTravIds;      // the counter of traversal IDs
     float               DelayTarget;   // the target required times
 
diff --git a/src/map/fpga/fpgaTime.c b/src/map/fpga/fpgaTime.c
index 76109b6e..380ff592 100644
--- a/src/map/fpga/fpgaTime.c
+++ b/src/map/fpga/fpgaTime.c
@@ -87,13 +87,34 @@ float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p )
 {
     float fRequired;
     int i;
+    if ( p->fLatchPaths && p->nLatches == 0 )
+    {
+        printf( "Delay optimization of latch path is not performed because there is no latches.\n" );
+        p->fLatchPaths = 0;
+    }
     // get the critical PO arrival time
     fRequired = -FPGA_FLOAT_LARGE;
-    for ( i = 0; i < p->nOutputs; i++ )
+    if ( p->fLatchPaths )
     {
-        if ( Fpga_NodeIsConst(p->pOutputs[i]) )
-            continue;
-        fRequired = FPGA_MAX( fRequired, Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
+        for ( i = p->nOutputs - p->nLatches; i < p->nOutputs; i++ )
+        {
+            if ( Fpga_NodeIsConst(p->pOutputs[i]) )
+                continue;
+            fRequired = FPGA_MAX( fRequired, Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
+//            printf( " %5.1f", Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
+        }
+//        printf( "Required latches = %5.1f\n", fRequired );
+    }
+    else
+    {
+        for ( i = 0; i < p->nOutputs; i++ )
+        {
+            if ( Fpga_NodeIsConst(p->pOutputs[i]) )
+                continue;
+            fRequired = FPGA_MAX( fRequired, Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
+//            printf( " %5.1f", Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
+        }
+//        printf( "Required outputs = %5.1f\n", fRequired );
     }
     return fRequired;
 }
@@ -148,10 +169,23 @@ void Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired )
     for ( i = 0; i < p->vAnds->nSize; i++ )
         p->vAnds->pArray[i]->tRequired = FPGA_FLOAT_LARGE;
     // set the required times for the POs
-    for ( i = 0; i < p->nOutputs; i++ )
-        Fpga_Regular(p->pOutputs[i])->tRequired = fRequired;
+    if ( p->fLatchPaths )
+        for ( i = p->nOutputs - p->nLatches; i < p->nOutputs; i++ )
+            Fpga_Regular(p->pOutputs[i])->tRequired = fRequired;
+    else
+        for ( i = 0; i < p->nOutputs; i++ )
+            Fpga_Regular(p->pOutputs[i])->tRequired = fRequired;
     // collect nodes reachable from POs in the DFS order through the best cuts
     Fpga_TimePropagateRequired( p, p->vMapping );
+/*
+    {
+        int Counter = 0;
+        for ( i = 0; i < p->vAnds->nSize; i++ )
+            if ( p->vAnds->pArray[i]->tRequired > FPGA_FLOAT_LARGE - 100 )
+                Counter++;
+        printf( "The number of nodes with large required times = %d.\n", Counter );
+    }
+*/
 }
 
 /**Function*************************************************************