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-rw-r--r--src/base/io/io.c64
-rw-r--r--src/base/io/ioReadBaf.c4
-rw-r--r--src/base/io/ioReadBench.c2
-rw-r--r--src/base/io/ioReadBlif.c2
-rw-r--r--src/base/io/ioUtil.c4
-rw-r--r--src/base/io/ioWriteDot.c25
-rw-r--r--src/base/io/ioWriteList.c82
7 files changed, 171 insertions, 12 deletions
diff --git a/src/base/io/io.c b/src/base/io/io.c
index 9c1b94ab..7a661664 100644
--- a/src/base/io/io.c
+++ b/src/base/io/io.c
@@ -40,6 +40,7 @@ static int IoCommandReadTruth ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBaf ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBlif ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteBench ( Abc_Frame_t * pAbc, int argc, char **argv );
+static int IoCommandWriteCellNet( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteCnf ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteDot ( Abc_Frame_t * pAbc, int argc, char **argv );
static int IoCommandWriteEqn ( Abc_Frame_t * pAbc, int argc, char **argv );
@@ -84,6 +85,7 @@ void Io_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "I/O", "write_baf", IoCommandWriteBaf, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_blif", IoCommandWriteBlif, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_bench", IoCommandWriteBench, 0 );
+ Cmd_CommandAdd( pAbc, "I/O", "write_cellnet", IoCommandWriteCellNet, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_cnf", IoCommandWriteCnf, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_dot", IoCommandWriteDot, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_eqn", IoCommandWriteEqn, 0 );
@@ -1189,6 +1191,68 @@ usage:
SeeAlso []
***********************************************************************/
+int IoCommandWriteCellNet( Abc_Frame_t * pAbc, int argc, char **argv )
+{
+ Abc_Ntk_t * pNtk;
+ char * FileName;
+ int c;
+ extern void Io_WriteCellNet( Abc_Ntk_t * pNtk, char * pFileName );
+
+ Extra_UtilGetoptReset();
+ while ( ( c = Extra_UtilGetopt( argc, argv, "h" ) ) != EOF )
+ {
+ switch ( c )
+ {
+ case 'h':
+ goto usage;
+ default:
+ goto usage;
+ }
+ }
+
+ pNtk = pAbc->pNtkCur;
+ if ( pNtk == NULL )
+ {
+ fprintf( pAbc->Out, "Empty network.\n" );
+ return 0;
+ }
+
+ if ( argc != globalUtilOptind + 1 )
+ {
+ goto usage;
+ }
+ // get the input file name
+ FileName = argv[globalUtilOptind];
+
+ if ( !Abc_NtkIsLogic(pNtk) )
+ {
+ fprintf( pAbc->Out, "The network should be a logic network (if it an AIG, use command \"logic\")\n" );
+ return 0;
+ }
+
+ // derive the netlist
+ Io_WriteCellNet( pNtk, FileName );
+ return 0;
+
+usage:
+ fprintf( pAbc->Err, "usage: write_cellnet [-h] <file>\n" );
+ fprintf( pAbc->Err, "\t write the network is the cellnet format\n" );
+ fprintf( pAbc->Err, "\t-h : print the help massage\n" );
+ fprintf( pAbc->Err, "\tfile : the name of the file to write\n" );
+ return 1;
+}
+
+/**Function*************************************************************
+
+ Synopsis []
+
+ Description []
+
+ SideEffects []
+
+ SeeAlso []
+
+***********************************************************************/
int IoCommandWriteCnf( Abc_Frame_t * pAbc, int argc, char **argv )
{
char * FileName;
diff --git a/src/base/io/ioReadBaf.c b/src/base/io/ioReadBaf.c
index 15d75ba8..a6e0c2e2 100644
--- a/src/base/io/ioReadBaf.c
+++ b/src/base/io/ioReadBaf.c
@@ -100,10 +100,10 @@ Abc_Ntk_t * Io_ReadBaf( char * pFileName, int fCheck )
pObj = Abc_NtkCreateLatch(pNtkNew);
Abc_ObjAssignName( pObj, pCur, NULL ); while ( *pCur++ );
- pNode0 = Abc_NtkCreateBo(pNtkNew);
+ pNode0 = Abc_NtkCreateBi(pNtkNew);
Abc_ObjAssignName( pNode0, pCur, NULL ); while ( *pCur++ );
- pNode1 = Abc_NtkCreateBi(pNtkNew);
+ pNode1 = Abc_NtkCreateBo(pNtkNew);
Abc_ObjAssignName( pNode1, pCur, NULL ); while ( *pCur++ );
Vec_PtrPush( vNodes, pNode1 );
diff --git a/src/base/io/ioReadBench.c b/src/base/io/ioReadBench.c
index aa7f82e3..72dd2b52 100644
--- a/src/base/io/ioReadBench.c
+++ b/src/base/io/ioReadBench.c
@@ -142,6 +142,8 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p )
Abc_ObjSetData( pNode, Abc_SopCreateBuf(pNtk->pManFunc) );
else if ( strcmp(pType, "NOT") == 0 )
Abc_ObjSetData( pNode, Abc_SopCreateInv(pNtk->pManFunc) );
+ else if ( strncmp(pType, "MUX", 3) == 0 )
+ Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "1-0 1\n-11 1\n") );
else
{
printf( "Cannot determine gate type \"%s\" in line %d.\n", pType, Extra_FileReaderGetLineNumber(p, 0) );
diff --git a/src/base/io/ioReadBlif.c b/src/base/io/ioReadBlif.c
index 8b7e015b..d7f456ff 100644
--- a/src/base/io/ioReadBlif.c
+++ b/src/base/io/ioReadBlif.c
@@ -354,7 +354,7 @@ int Io_ReadBlifNetworkAsserts( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens )
***********************************************************************/
int Io_ReadBlifNetworkLatch( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens )
-{
+{
Abc_Ntk_t * pNtk = p->pNtkCur;
Abc_Obj_t * pLatch;
int ResetValue;
diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c
index f2f07b14..dff27dd1 100644
--- a/src/base/io/ioUtil.c
+++ b/src/base/io/ioUtil.c
@@ -120,13 +120,13 @@ Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO )
// get the LI net
pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI );
// add the BO terminal
- pTerm = Abc_NtkCreateBo( pNtk );
+ pTerm = Abc_NtkCreateBi( pNtk );
Abc_ObjAddFanin( pTerm, pNet );
// add the latch box
pLatch = Abc_NtkCreateLatch( pNtk );
Abc_ObjAddFanin( pLatch, pTerm );
// add the BI terminal
- pTerm = Abc_NtkCreateBi( pNtk );
+ pTerm = Abc_NtkCreateBo( pNtk );
Abc_ObjAddFanin( pTerm, pLatch );
// get the LO net
pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO );
diff --git a/src/base/io/ioWriteDot.c b/src/base/io/ioWriteDot.c
index 05539c40..3cc3fcfe 100644
--- a/src/base/io/ioWriteDot.c
+++ b/src/base/io/ioWriteDot.c
@@ -19,7 +19,9 @@
***********************************************************************/
#include "io.h"
-#include "seqInt.h"
+#include "main.h"
+#include "mio.h"
+//#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@@ -292,6 +294,10 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
{
if ( Abc_ObjFaninNum(pNode) == 0 )
continue;
+
+ if ( Abc_ObjIsBo(pNode) )
+ continue;
+
if ( fMulti && Abc_ObjIsNode(pNode) )
{
Vec_Ptr_t * vSuper;
@@ -305,6 +311,10 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
pFanin = Abc_ObjRegular(pFanin);
if ( !pFanin->fMarkC )
continue;
+
+ if ( Abc_ObjIsBi(pFanin) )
+ continue;
+
fprintf( pFile, "Node%d", pNode->Id );
fprintf( pFile, " -> " );
fprintf( pFile, "Node%d%s", pFanin->Id, (Abc_ObjIsLatch(pFanin)? "_out":"") );
@@ -316,7 +326,7 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
continue;
}
// generate the edge from this node to the next
- if ( Abc_ObjFanin0(pNode)->fMarkC )
+ if ( Abc_ObjFanin0(pNode)->fMarkC && !Abc_ObjIsBi(Abc_ObjFanin0(pNode)) )
{
fprintf( pFile, "Node%d%s", pNode->Id, (Abc_ObjIsLatch(pNode)? "_in":"") );
fprintf( pFile, " -> " );
@@ -331,7 +341,7 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
if ( Abc_ObjFaninNum(pNode) == 1 )
continue;
// generate the edge from this node to the next
- if ( Abc_ObjFanin1(pNode)->fMarkC )
+ if ( Abc_ObjFanin1(pNode)->fMarkC && !Abc_ObjIsBi(Abc_ObjFanin1(pNode)) )
{
fprintf( pFile, "Node%d", pNode->Id );
fprintf( pFile, " -> " );
@@ -392,7 +402,7 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds;
int Limit = 300;
- assert( !Abc_NtkHasAig(pNtk) );
+ assert( !Abc_NtkIsStrash(pNtk) );
if ( vNodes->nSize < 1 )
{
@@ -606,7 +616,7 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMin );
- // generat the PO nodes
+ // generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCi(pNode) )
@@ -653,6 +663,11 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
{
if ( !Abc_ObjFanin0(pNode)->fMarkC )
continue;
+
+ // added to fix the bug after adding boxes
+ if ( Abc_ObjIsBo(pNode) || Abc_ObjIsBi(pFanin) )
+ continue;
+
// generate the edge from this node to the next
fprintf( pFile, "Node%d%s", pNode->Id, (Abc_ObjIsLatch(pNode)? "_in":"") );
fprintf( pFile, " -> " );
diff --git a/src/base/io/ioWriteList.c b/src/base/io/ioWriteList.c
index c2bea884..a92c2eff 100644
--- a/src/base/io/ioWriteList.c
+++ b/src/base/io/ioWriteList.c
@@ -19,7 +19,7 @@
***********************************************************************/
#include "io.h"
-#include "seqInt.h"
+//#include "seqInt.h"
/*
-------- Original Message --------
@@ -159,7 +159,8 @@ void Io_WriteListEdge( FILE * pFile, Abc_Obj_t * pObj )
{
fprintf( pFile, " %s", Abc_ObjName(pFanout) );
fprintf( pFile, " ([%s_to_", Abc_ObjName(pObj) );
- fprintf( pFile, "%s] = %d)", Abc_ObjName(pFanout), Seq_ObjFanoutL(pObj, pFanout) );
+// fprintf( pFile, "%s] = %d)", Abc_ObjName(pFanout), Seq_ObjFanoutL(pObj, pFanout) );
+ fprintf( pFile, "%s] = %d)", Abc_ObjName(pFanout), 0 );
if ( i != Abc_ObjFanoutNum(pObj) - 1 )
fprintf( pFile, "," );
}
@@ -204,6 +205,83 @@ void Io_WriteListHost( FILE * pFile, Abc_Ntk_t * pNtk )
}
+/**Function*************************************************************
+
+ Synopsis [Writes the adjacency list for a sequential AIG.]
+
+ Description []
+
+ SideEffects []
+
+ SeeAlso []
+
+***********************************************************************/
+void Io_WriteCellNet( Abc_Ntk_t * pNtk, char * pFileName )
+{
+ FILE * pFile;
+ Abc_Obj_t * pObj, * pFanout;
+ int i, k;
+
+ assert( Abc_NtkIsLogic(pNtk) );
+
+ // start the output stream
+ pFile = fopen( pFileName, "w" );
+ if ( pFile == NULL )
+ {
+ fprintf( stdout, "Io_WriteCellNet(): Cannot open the output file \"%s\".\n", pFileName );
+ return;
+ }
+
+ fprintf( pFile, "# CellNet file for network \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
+
+ // the only tricky part with writing is handling latches:
+ // each latch comes with (a) single-input latch-input node, (b) latch proper, (c) single-input latch-output node
+ // we arbitrarily decide to use the interger ID of the latch-input node to represent the latch in the file
+ // (this ID is used for both the cell and the net driven by that cell)
+
+ // write the PIs
+ Abc_NtkForEachPi( pNtk, pObj, i )
+ fprintf( pFile, "cell %d is 0\n", pObj->Id );
+ // write the POs
+ Abc_NtkForEachPo( pNtk, pObj, i )
+ fprintf( pFile, "cell %d is 1\n", pObj->Id );
+ // write the latches (use the ID of latch input)
+ Abc_NtkForEachLatch( pNtk, pObj, i )
+ fprintf( pFile, "cell %d is 2\n", Abc_ObjFanin0(pObj)->Id );
+ // write the logic nodes
+ Abc_NtkForEachNode( pNtk, pObj, i )
+ fprintf( pFile, "cell %d is %d\n", pObj->Id, 3+Abc_ObjFaninNum(pObj) );
+
+ // write the nets driven by PIs
+ Abc_NtkForEachPi( pNtk, pObj, i )
+ {
+ fprintf( pFile, "net %d %d 0", pObj->Id, pObj->Id );
+ Abc_ObjForEachFanout( pObj, pFanout, k )
+ fprintf( pFile, " %d %d", pFanout->Id, 1 + Abc_ObjFanoutFaninNum(pFanout, pObj) );
+ fprintf( pFile, "\n" );
+ }
+ // write the nets driven by latches
+ Abc_NtkForEachLatch( pNtk, pObj, i )
+ {
+ fprintf( pFile, "net %d %d 0", Abc_ObjFanin0(pObj)->Id, Abc_ObjFanin0(pObj)->Id );
+ pObj = Abc_ObjFanout0(pObj);
+ Abc_ObjForEachFanout( pObj, pFanout, k )
+ fprintf( pFile, " %d %d", pFanout->Id, 1 + Abc_ObjFanoutFaninNum(pFanout, pObj) );
+ fprintf( pFile, "\n" );
+ }
+ // write the nets driven by nodes
+ Abc_NtkForEachNode( pNtk, pObj, i )
+ {
+ fprintf( pFile, "net %d %d 0", pObj->Id, pObj->Id );
+ Abc_ObjForEachFanout( pObj, pFanout, k )
+ fprintf( pFile, " %d %d", pFanout->Id, 1 + Abc_ObjFanoutFaninNum(pFanout, pObj) );
+ fprintf( pFile, "\n" );
+ }
+
+ fprintf( pFile, "\n" );
+ fclose( pFile );
+}
+
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
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