diff options
Diffstat (limited to 'src/base/io')
-rw-r--r-- | src/base/io/io.c | 264 | ||||
-rw-r--r-- | src/base/io/ioReadBlif.c | 18 | ||||
-rw-r--r-- | src/base/io/ioWriteVer.c | 84 |
3 files changed, 356 insertions, 10 deletions
diff --git a/src/base/io/io.c b/src/base/io/io.c index 614fa812..6da1f4d8 100644 --- a/src/base/io/io.c +++ b/src/base/io/io.c @@ -32,6 +32,8 @@ static int IoCommandReadBench ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadEdif ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadEqn ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadVerilog ( Abc_Frame_t * pAbc, int argc, char **argv ); +static int IoCommandReadVer ( Abc_Frame_t * pAbc, int argc, char **argv ); +static int IoCommandReadVerLib ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadPla ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadTruth ( Abc_Frame_t * pAbc, int argc, char **argv ); @@ -45,6 +47,7 @@ static int IoCommandWriteGml ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteList ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWritePla ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv ); +static int IoCommandWriteVerLib ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteCounter( Abc_Frame_t * pAbc, int argc, char **argv ); //////////////////////////////////////////////////////////////////////// @@ -71,6 +74,8 @@ void Io_Init( Abc_Frame_t * pAbc ) Cmd_CommandAdd( pAbc, "I/O", "read_edif", IoCommandReadEdif, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_eqn", IoCommandReadEqn, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_verilog", IoCommandReadVerilog, 1 ); + Cmd_CommandAdd( pAbc, "I/O", "read_ver", IoCommandReadVer, 1 ); + Cmd_CommandAdd( pAbc, "I/O", "read_verlib", IoCommandReadVerLib, 0 ); Cmd_CommandAdd( pAbc, "I/O", "read_pla", IoCommandReadPla, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_truth", IoCommandReadTruth, 1 ); @@ -84,6 +89,7 @@ void Io_Init( Abc_Frame_t * pAbc ) Cmd_CommandAdd( pAbc, "I/O", "write_list", IoCommandWriteList, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_pla", IoCommandWritePla, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_verilog", IoCommandWriteVerilog, 0 ); + Cmd_CommandAdd( pAbc, "I/O", "write_verlib", IoCommandWriteVerLib, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_counter", IoCommandWriteCounter, 0 ); } @@ -659,6 +665,209 @@ usage: SeeAlso [] ***********************************************************************/ +int IoCommandReadVer( Abc_Frame_t * pAbc, int argc, char ** argv ) +{ + Abc_Ntk_t * pNtk, * pTemp; + st_table * tDesign; + char * FileName; + FILE * pFile; + int fCheck; + int c; + extern st_table * Ver_ParseFile( char * pFileName, st_table * pGateLib, int fCheck ); + + fCheck = 1; + Extra_UtilGetoptReset(); + while ( ( c = Extra_UtilGetopt( argc, argv, "ch" ) ) != EOF ) + { + switch ( c ) + { + case 'c': + fCheck ^= 1; + break; + case 'h': + goto usage; + default: + goto usage; + } + } + + if ( argc != globalUtilOptind + 1 ) + { + goto usage; + } + + // get the input file name + FileName = argv[globalUtilOptind]; + if ( (pFile = fopen( FileName, "r" )) == NULL ) + { + fprintf( pAbc->Err, "Cannot open input file \"%s\". ", FileName ); + if ( FileName = Extra_FileGetSimilarName( FileName, ".mv", ".blif", ".pla", ".eqn", ".bench" ) ) + fprintf( pAbc->Err, "Did you mean \"%s\"?", FileName ); + fprintf( pAbc->Err, "\n" ); + return 1; + } + fclose( pFile ); + + // set the new network + tDesign = Ver_ParseFile( FileName, Abc_FrameReadLibVer(), fCheck ); + if ( tDesign == NULL ) + { + fprintf( pAbc->Err, "Reading network from the verilog file has failed.\n" ); + return 1; + } + + if ( st_count(tDesign) == 1 ) + { + st_generator * gen; + char * pName; + // find the network + st_foreach_item( tDesign, gen, (char**)&pName, (char**)&pNtk ) + { + st_free_gen(gen); + break; + } + st_free_table( tDesign ); + + // convert it into a logic network + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); + Abc_NtkDelete( pTemp ); + if ( pNtk == NULL ) + { + fprintf( pAbc->Err, "Converting to logic network after reading has failed.\n" ); + return 1; + } + // replace the current network + Abc_FrameReplaceCurrentNetwork( pAbc, pNtk ); + } + else + { + printf( "The design includes more than one module and is currently not used.\n" ); + } + + return 0; + +usage: + fprintf( pAbc->Err, "usage: read_ver [-ch] <file>\n" ); + fprintf( pAbc->Err, "\t read a network in structural verilog (using current library)\n" ); + fprintf( pAbc->Err, "\t-c : toggle network check after reading [default = %s]\n", fCheck? "yes":"no" ); + fprintf( pAbc->Err, "\t-h : prints the command summary\n" ); + fprintf( pAbc->Err, "\tfile : the name of a file to read\n" ); + return 1; +} + +/**Function************************************************************* + + Synopsis [] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +int IoCommandReadVerLib( Abc_Frame_t * pAbc, int argc, char ** argv ) +{ + Abc_Ntk_t * pNtk, * pTemp; + st_table * tDesign; + char * FileName; + FILE * pFile; + int fCheck; + int c; + extern st_table * Ver_ParseFile( char * pFileName, st_table * pGateLib, int fCheck ); + extern void Ver_ParseFreeLibrary( st_table * pLibVer ); + + fCheck = 1; + Extra_UtilGetoptReset(); + while ( ( c = Extra_UtilGetopt( argc, argv, "ch" ) ) != EOF ) + { + switch ( c ) + { + case 'c': + fCheck ^= 1; + break; + case 'h': + goto usage; + default: + goto usage; + } + } + + if ( argc != globalUtilOptind + 1 ) + { + goto usage; + } + + // get the input file name + FileName = argv[globalUtilOptind]; + if ( (pFile = fopen( FileName, "r" )) == NULL ) + { + fprintf( pAbc->Err, "Cannot open input file \"%s\". ", FileName ); + if ( FileName = Extra_FileGetSimilarName( FileName, ".mv", ".blif", ".pla", ".eqn", ".bench" ) ) + fprintf( pAbc->Err, "Did you mean \"%s\"?", FileName ); + fprintf( pAbc->Err, "\n" ); + return 1; + } + fclose( pFile ); + + // set the new network + tDesign = Ver_ParseFile( FileName, NULL, fCheck ); + if ( tDesign == NULL ) + { + fprintf( pAbc->Err, "Reading library from the verilog file has failed.\n" ); + return 1; + } + printf( "The library contains %d gates.\n", st_count(tDesign) ); + + // convert gates into AIGs + { + st_table * tLibrary; + st_generator * gen; + char * pName; + // transform the gates into the library AIGs + tLibrary = st_init_table( strcmp, st_strhash ); + st_foreach_item( tDesign, gen, (char**)&pName, (char**)&pNtk ) + { + // convert the netlist into SOP logic network + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); + Abc_NtkDelete( pTemp ); + // perform structural hashing + pNtk = Abc_NtkStrash( pTemp = pNtk, 0, 1 ); + Abc_NtkDelete( pTemp ); + // insert the new network into the new library + st_insert( tLibrary, pNtk->pName, (char *)pNtk ); + } + st_free_table( tDesign ); + + // free old library + if ( Abc_FrameReadLibVer() ) + Ver_ParseFreeLibrary( Abc_FrameReadLibVer() ); + // read new library + Abc_FrameSetLibVer( tLibrary ); + } + + return 0; + +usage: + fprintf( pAbc->Err, "usage: read_verlib [-ch] <file>\n" ); + fprintf( pAbc->Err, "\t read a gate library in structural verilog\n" ); + fprintf( pAbc->Err, "\t-c : toggle network check after reading [default = %s]\n", fCheck? "yes":"no" ); + fprintf( pAbc->Err, "\t-h : prints the command summary\n" ); + fprintf( pAbc->Err, "\tfile : the name of a file to read\n" ); + return 1; +} + +/**Function************************************************************* + + Synopsis [] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ int IoCommandReadPla( Abc_Frame_t * pAbc, int argc, char ** argv ) { Abc_Ntk_t * pNtk, * pTemp; @@ -1472,6 +1681,61 @@ usage: SeeAlso [] ***********************************************************************/ +int IoCommandWriteVerLib( Abc_Frame_t * pAbc, int argc, char **argv ) +{ + st_table * tLibrary; + char * FileName; + int c; + extern void Io_WriteVerilogLibrary( st_table * tLibrary, char * pFileName ); + + Extra_UtilGetoptReset(); + while ( ( c = Extra_UtilGetopt( argc, argv, "h" ) ) != EOF ) + { + switch ( c ) + { + case 'h': + goto usage; + default: + goto usage; + } + } + + if ( argc != globalUtilOptind + 1 ) + { + goto usage; + } + // get the input file name + FileName = argv[globalUtilOptind]; + + // derive the netlist + tLibrary = Abc_FrameReadLibVer(); + if ( tLibrary == NULL ) + { + fprintf( pAbc->Out, "Verilog library is not specified.\n" ); + return 0; + } + Io_WriteVerilogLibrary( tLibrary, FileName ); + return 0; + +usage: + fprintf( pAbc->Err, "usage: write_verlib [-h] <file>\n" ); + fprintf( pAbc->Err, "\t write the current verilog library\n" ); + fprintf( pAbc->Err, "\t-h : print the help massage\n" ); + fprintf( pAbc->Err, "\tfile : the name of the file to write\n" ); + return 1; +} + +/**Function************************************************************* + + Synopsis [] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ int IoCommandWriteCounter( Abc_Frame_t * pAbc, int argc, char **argv ) { Abc_Ntk_t * pNtk; diff --git a/src/base/io/ioReadBlif.c b/src/base/io/ioReadBlif.c index 11dd2db1..ade9051f 100644 --- a/src/base/io/ioReadBlif.c +++ b/src/base/io/ioReadBlif.c @@ -43,6 +43,7 @@ struct Io_ReadBlif_t_ // the error message FILE * Output; // the output stream char sError[1000]; // the error string generated during parsing + int fError; // set to 1 when error occurs }; static Io_ReadBlif_t * Io_ReadBlifFile( char * pFileName ); @@ -182,7 +183,7 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p ) return NULL; } } - else + else if ( !p->fError ) Abc_NtkFinalizeRead( pNtkMaster ); // return the master network return pNtkMaster; @@ -273,7 +274,11 @@ Abc_Ntk_t * Io_ReadBlifNetworkOne( Io_ReadBlif_t * p ) if ( p->vTokens == NULL ) // some files do not have ".end" in the end break; if ( fStatus == 1 ) + { + Extra_ProgressBarStop( pProgress ); + Abc_NtkDelete( pNtk ); return NULL; + } } if ( p->pNtkMaster == NULL ) Extra_ProgressBarStop( pProgress ); @@ -487,6 +492,16 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) // set the pointer to the functionality of the node Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, p->vCubes->pArray) ); + // check the size + if ( Abc_ObjFaninNum(pNode) != Abc_SopGetVarNum(Abc_ObjData(pNode)) ) + { + p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); + sprintf( p->sError, "The number of fanins (%d) of node %s is different from SOP size (%d).", + Abc_ObjFaninNum(pNode), Abc_ObjName(Abc_ObjFanout(pNode,0)), Abc_SopGetVarNum(Abc_ObjData(pNode)) ); + Io_ReadBlifPrintErrorMessage( p ); + return 1; + } + // return the last array of tokens *pvTokens = vTokens; return 0; @@ -735,6 +750,7 @@ int Io_ReadBlifNetworkDefaultInputArrival( Io_ReadBlif_t * p, Vec_Ptr_t * vToken ***********************************************************************/ void Io_ReadBlifPrintErrorMessage( Io_ReadBlif_t * p ) { + p->fError = 1; if ( p->LineCur == 0 ) // the line number is not given fprintf( p->Output, "%s: %s\n", p->pFileName, p->sError ); else // print the error message with the line number diff --git a/src/base/io/ioWriteVer.c b/src/base/io/ioWriteVer.c index 902219aa..594bf4eb 100644 --- a/src/base/io/ioWriteVer.c +++ b/src/base/io/ioWriteVer.c @@ -36,6 +36,7 @@ static void Io_WriteVerilogNodes( FILE * pFile, Abc_Ntk_t * pNtk ); static void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ); static int Io_WriteVerilogCheckNtk( Abc_Ntk_t * pNtk ); static char * Io_WriteVerilogGetName( Abc_Obj_t * pObj ); +static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// @@ -73,6 +74,7 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName ) } // write the equations for the network + fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); Io_WriteVerilogInt( pFile, pNtk ); fprintf( pFile, "\n" ); fclose( pFile ); @@ -80,6 +82,49 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName ) /**Function************************************************************* + Synopsis [Write verilog.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Io_WriteVerilogLibrary( st_table * tLibrary, char * pFileName ) +{ + FILE * pFile; + st_generator * gen; + Abc_Ntk_t * pNtk, * pNetlist; + char * pName; + + // start the output stream + pFile = fopen( pFileName, "w" ); + if ( pFile == NULL ) + { + fprintf( stdout, "Io_WriteVerilogLibrary(): Cannot open the output file \"%s\".\n", pFileName ); + return; + } + + fprintf( pFile, "// Verilog library \"%s\" written by ABC on %s\n", pFileName, Extra_TimeStamp() ); + fprintf( pFile, "\n" ); + // write modules + st_foreach_item( tLibrary, gen, (char**)&pName, (char**)&pNtk ) + { + // create netlist + pNetlist = Abc_NtkLogicToNetlist( pNtk, 0 ); + // write the equations for the network + Io_WriteVerilogInt( pFile, pNetlist ); + fprintf( pFile, "\n" ); + // delete the netlist + Abc_NtkDelete( pNetlist ); + } + + fclose( pFile ); +} + +/**Function************************************************************* + Synopsis [Writes verilog.] Description [] @@ -92,7 +137,6 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName ) void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ) { // write inputs and outputs - fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) ); Io_WriteVerilogPis( pFile, pNtk, 3 ); fprintf( pFile, ",\n " ); @@ -111,9 +155,12 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ) Io_WriteVerilogRegs( pFile, pNtk, 4 ); fprintf( pFile, ";\n" ); } + if ( Io_WriteVerilogWiresCount(pNtk) > 0 ) + { fprintf( pFile, " wire" ); Io_WriteVerilogWires( pFile, pNtk, 4 ); fprintf( pFile, ";\n" ); + } // write the nodes if ( Abc_NtkHasMapping(pNtk) ) Io_WriteVerilogGates( pFile, pNtk ); @@ -205,7 +252,7 @@ void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) /**Function************************************************************* - Synopsis [Writes the wires.] + Synopsis [Counts the number of wires.] Description [] @@ -214,15 +261,10 @@ void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) SeeAlso [] ***********************************************************************/ -void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) +int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ) { Abc_Obj_t * pTerm, * pNet; - int LineLength; - int AddedLength; - int NameCounter; - int i, Counter, nNodes; - - // count the number of wires + int i, nNodes; nNodes = Abc_NtkLatchNum(pNtk); Abc_NtkForEachNode( pNtk, pTerm, i ) { @@ -233,6 +275,30 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) continue; nNodes++; } + return nNodes; +} + +/**Function************************************************************* + + Synopsis [Writes the wires.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) +{ + Abc_Obj_t * pTerm, * pNet; + int LineLength; + int AddedLength; + int NameCounter; + int i, Counter, nNodes; + + // count the number of wires + nNodes = Io_WriteVerilogWiresCount( pNtk ); // write the wires Counter = 0; |