1 files changed, 75 insertions, 9 deletions

diff --git a/src/base/io/ioWriteVer.c b/src/base/io/ioWriteVer.c
index 902219aa..594bf4eb 100644
--- a/src/base/io/ioWriteVer.c
+++ b/src/base/io/ioWriteVer.c
@@ -36,6 +36,7 @@ static void Io_WriteVerilogNodes( FILE * pFile, Abc_Ntk_t * pNtk );
 static void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk );
 static int Io_WriteVerilogCheckNtk( Abc_Ntk_t * pNtk );
 static char * Io_WriteVerilogGetName( Abc_Obj_t * pObj );
+static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk );
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -73,6 +74,7 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
     }
 
     // write the equations for the network
+    fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
     Io_WriteVerilogInt( pFile, pNtk );
     fprintf( pFile, "\n" );
     fclose( pFile );
@@ -80,6 +82,49 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
 
 /**Function*************************************************************
 
+  Synopsis    [Write verilog.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Io_WriteVerilogLibrary( st_table * tLibrary, char * pFileName )
+{
+    FILE * pFile;
+    st_generator * gen;
+    Abc_Ntk_t * pNtk, * pNetlist;
+    char * pName;
+
+    // start the output stream
+    pFile = fopen( pFileName, "w" );
+    if ( pFile == NULL )
+    {
+        fprintf( stdout, "Io_WriteVerilogLibrary(): Cannot open the output file \"%s\".\n", pFileName );
+        return;
+    }
+
+    fprintf( pFile, "// Verilog library \"%s\" written by ABC on %s\n", pFileName, Extra_TimeStamp() );
+    fprintf( pFile, "\n" );
+    // write modules
+    st_foreach_item( tLibrary, gen, (char**)&pName, (char**)&pNtk )
+    {
+        // create netlist
+        pNetlist = Abc_NtkLogicToNetlist( pNtk, 0 );
+        // write the equations for the network
+        Io_WriteVerilogInt( pFile, pNetlist );
+        fprintf( pFile, "\n" );
+        // delete the netlist
+        Abc_NtkDelete( pNetlist );
+    }
+
+    fclose( pFile );
+}
+
+/**Function*************************************************************
+
   Synopsis    [Writes verilog.]
 
   Description []
@@ -92,7 +137,6 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
 void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk )
 {
     // write inputs and outputs
-    fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
     fprintf( pFile, "module %s ( gclk,\n   ", Abc_NtkName(pNtk) );
     Io_WriteVerilogPis( pFile, pNtk, 3 );
     fprintf( pFile, ",\n   " );
@@ -111,9 +155,12 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk )
     Io_WriteVerilogRegs( pFile, pNtk, 4 );
     fprintf( pFile, ";\n" );
     }
+    if ( Io_WriteVerilogWiresCount(pNtk) > 0 )
+    {
     fprintf( pFile, "  wire" );
     Io_WriteVerilogWires( pFile, pNtk, 4 );
     fprintf( pFile, ";\n" );
+    }
     // write the nodes
     if ( Abc_NtkHasMapping(pNtk) )
         Io_WriteVerilogGates( pFile, pNtk );
@@ -205,7 +252,7 @@ void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
 
 /**Function*************************************************************
 
-  Synopsis    [Writes the wires.]
+  Synopsis    [Counts the number of wires.]
 
   Description []
                
@@ -214,15 +261,10 @@ void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
   SeeAlso     []
 
 ***********************************************************************/
-void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
+int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk )
 {
     Abc_Obj_t * pTerm, * pNet;
-    int LineLength;
-    int AddedLength;
-    int NameCounter;
-    int i, Counter, nNodes;
-
-    // count the number of wires
+    int i, nNodes;
     nNodes = Abc_NtkLatchNum(pNtk);
     Abc_NtkForEachNode( pNtk, pTerm, i )
     {
@@ -233,6 +275,30 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
             continue;
         nNodes++;
     }
+    return nNodes;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Writes the wires.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
+{
+    Abc_Obj_t * pTerm, * pNet;
+    int LineLength;
+    int AddedLength;
+    int NameCounter;
+    int i, Counter, nNodes;
+
+    // count the number of wires
+    nNodes = Io_WriteVerilogWiresCount( pNtk );
 
     // write the wires
     Counter = 0;